Embedded Supercomputing with Reconfigurable Hardware

具有可重构硬件的嵌入式超级计算

• 批准号: RGPIN-2016-06665
• 负责人: Lemieux, Guy
• 金额: $ 2.99万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2020
• 资助国家: 加拿大
• 起止时间: 2020-01-01 至 2021-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=710346
• 关键词: Embedded; Supercomputing; Reconfigurable; Hardware

The way in which we use computing and how it influences our lives continues to evolve with our technological capability. High-performance computing is now available in devices smaller than our smartphones. The “Internet of Things” is a moniker for “plugging devices” into the network so that we may query and alter their state. In many cases, this also presumes they have some autonomous processing capability. Significant processing can be done directly on the end device whenever the energy, network bandwidth and response latency requirements demand it. However, specialized compute tasks are often offloaded to the cloud, when network the energy is lower than the compute energy and/or the result can be computed faster using dedicated accelerators. This research aims to improve processing speed and energy in standalone embedded devices and embedded in datacenters through the use of reconfigurable hardware devices known as Field-Programmable Gate Arrays (FPGAs). An FPGA is a high-capacity programmable logic chip, capable of implementing any user-designed digital circuit, including massively parallel computational systems. Modern FPGAs can host hundreds to thousands of processor cores and achieve more than 10 TeraFLOPs of performance. Despite this great performance potential, FPGAs remain extremely difficult to program by end users. To overcome the difficult-to-program reputation of FPGAs, researchers have invented the notion of overlay architectures, or simply overlays. In simple terms, an overlay is two parts: (1) an architecture, which is a predesigned parallel computer system mapped into an FPGA, and (2) a set of compiler-like CAD tools. An overlay architecture is usually described in VHDL or Verilog, and used to configure the FPGA. However, an overlay architecture cannot solve any problems because, like any computer system, it needs a “program” to run. Hence, compiler-like CAD tools are needed to map a user's program into the overlay architecture. These compiler-like CAD tools are very easy to use, being much like traditional C compilers for regular CPUs. As a result, overlays transform an FPGA from a difficult-to-program device into a custom-designed computer system that is very easy to program. This makes the TeraFLOPS level of performance in FPGAs accessible to end-users. The research described in this proposal involves the creation of new overlay architectures, new tools for mapping user applications into the overlays, and new tools for mapping overlays into FPGA devices themselves. This will enable new levels of performance and new capabilities for important modern applications such as image processing, computer vision, machine learning, medical diagnostics, and software-defined radio.

我们使用计算机的方式以及它如何影响我们的生活，随着我们的技术能力不断发展。现在，比我们的智能手机还小的设备上也可以实现高性能计算。“物联网”是“将设备插入网络”的绰号，这样我们就可以查询和改变它们的状态。在许多情况下，这还假定它们具有一些自主处理能力。只要能量、网络带宽和响应延迟需求需要，就可以直接在终端设备上进行重要的处理。然而，当网络能量低于计算能量和/或使用专用加速器可以更快地计算结果时，专门的计算任务通常会卸载到云上。