Towards Efficient Software-Defined Accelerator-Rich Systems
迈向高效的软件定义加速器丰富的系统
基本信息
- 批准号:RGPIN-2019-04613
- 负责人:
- 金额:$ 2.4万
- 依托单位:
- 依托单位国家:加拿大
- 项目类别:Discovery Grants Program - Individual
- 财政年份:2022
- 资助国家:加拿大
- 起止时间:2022-01-01 至 2023-12-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
With the significant slowdown of general-purpose CPU scaling, the computing industry has been actively exploring specialized and programmable hardware accelerators, such as GPUs and FPGAs, to bring orders-of-magnitude performance and energy gains for key applications such as machine learning, computational genomics, and scientific computing. While GPUs have already made a great success in the past decade, recently FPGAs have attracted increasing attention in datacenters: in the past year, Amazon, Alibaba, and Huawei all announced the public access of their FPGA-enabled cloud. However, there are two major challenges that impede the wide adoption of such heterogeneous systems with FPGAs in software applications. First, it is very difficult to program them since traditionally the use of FPGAs has been limited to a small group of hardware experts. Second, it is nontrivial to figure out whether a software application can get better performance on a system with FPGA or its strong competitor GPU. The long-term goal of this project is to enable the wide adoption of heterogeneous systems with FPGA accelerators in the vast software community, by developing efficient programming and runtime support for such systems to provide competitive performance, performance/watt, and/or performance/dollar. First, we will develop a software developer friendly programming framework that achieves efficient end-to-end system performance. To reduce the significant hardware expertise required by existing high-level synthesis (HLS) based accelerator designs, we plan to characterize common HLS programming patterns, automate their code transformation and design space exploration. Instead of focusing on a single accelerator design, we plan to provide system-level compilation and optimization that optimizes the communication between multiple accelerators, their memory system, and the host CPU cores. Second, we will develop an analytical model and program analysis tools to provide early-stage guidance in selecting FPGA or GPU acceleration for a given application. Our first step is to port widely recognized GPU (FPGA) benchmarks to FPGAs (GPUs), and quantitatively compare their performance. Based on the in-depth breakdown analysis, we will build an analytical model, develop program analysis tools and apply machine learning techniques to extract model factors from the application source code to guide the FPGA and GPU selection. The proposed research will develop critical technologies, reusable methodology and tools for efficient software-defined heterogeneous systems, to enable the software industry to continue scaling in post-Moore's law era. It will significantly accelerate the computing efficiency of driver applications that are key to Canada's economy and security, such as machine learning, personalized healthcare, scientific computing, and big data analytics. Moreover, it will provide many research and development opportunities to train our next-generation professionals.
随着通用CPU扩展的显著放缓,计算行业一直在积极探索专用和可编程硬件加速器,如GPU和FPGA,为机器学习、计算基因组学和科学计算等关键应用带来数量级的性能和能源收益。虽然GPU在过去十年中已经取得了巨大的成功,但最近FPGA在数据中心引起了越来越多的关注:在过去的一年里,亚马逊、阿里巴巴和华为都宣布他们的支持FPGA的云可以公开访问。然而,有两个主要的挑战阻碍了在软件应用中广泛采用这种具有现场可编程门阵列的异类系统。首先,编程非常困难,因为传统上,现场可编程门阵列的使用仅限于一小群硬件专家。其次,要弄清楚一个软件应用程序是否可以在配备了FPGA或其强大竞争对手GPU的系统上获得更好的性能,这并不是一件容易的事情。该项目的长期目标是通过开发高效的编程和运行时支持,以提供具有竞争力的性能、性能/瓦特和/或性能/美元,从而使具有现场可编程门阵列加速器的异类系统在广大软件社区得到广泛采用。首先,我们将开发一个软件开发人员友好的编程框架,以实现高效的端到端系统性能。为了减少现有基于高级综合(HLS)的加速器设计所需的大量硬件专业知识,我们计划表征常见的HLS编程模式,自动执行它们的代码转换,并设计空间探索。我们计划提供系统级编译和优化,以优化多个加速器、它们的存储系统和主机CPU核心之间的通信,而不是专注于单个加速器设计。其次,我们将开发分析模型和程序分析工具,以便在为特定应用选择FPGA或GPU加速时提供早期指导。我们的第一步是将广泛认可的GPU(FPGA)基准移植到FPGA(GPU),并定量比较它们的性能。在深入故障分析的基础上,我们将构建分析模型,开发程序分析工具,并应用机器学习技术从应用程序源代码中提取模型因素,以指导FPGA和GPU的选择。拟议的研究将为高效的软件定义的异构系统开发关键技术、可重复使用的方法和工具,使软件行业能够在后摩尔定律时代继续扩大规模。它将显著提高对加拿大经济和安全至关重要的驱动程序应用程序的计算效率,例如机器学习、个性化医疗保健、科学计算和大数据分析。此外,它还将提供许多研究和开发机会,以培训我们的下一代专业人员。
项目成果
期刊论文数量(0)
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专利数量(0)
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Fang, Zhenman其他文献
In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms
现代异构CPU-FPGA平台微架构深入分析
- DOI:
10.1145/3294054 - 发表时间:
2019 - 期刊:
- 影响因子:2.3
- 作者:
Choi, Young-Kyu;Cong, Jason;Fang, Zhenman;Hao, Yuchen;Reinman, Glenn;Wei, Peng - 通讯作者:
Wei, Peng
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs
- DOI:
10.1145/3514253 - 发表时间:
2022-12-01 - 期刊:
- 影响因子:2.3
- 作者:
Panchapakesan, Sathish;Fang, Zhenman;Li, Jian - 通讯作者:
Li, Jian
Fang, Zhenman的其他文献
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{{ truncateString('Fang, Zhenman', 18)}}的其他基金
Towards Efficient Software-Defined Accelerator-Rich Systems
迈向高效的软件定义加速器丰富的系统
- 批准号:
RGPIN-2019-04613 - 财政年份:2021
- 资助金额:
$ 2.4万 - 项目类别:
Discovery Grants Program - Individual
Towards Efficient Software-Defined Accelerator-Rich Systems
迈向高效的软件定义加速器丰富的系统
- 批准号:
RGPIN-2019-04613 - 财政年份:2020
- 资助金额:
$ 2.4万 - 项目类别:
Discovery Grants Program - Individual
Intelligent Computing Memory Systems for Data-Intensive Applications
适用于数据密集型应用的智能计算内存系统
- 批准号:
552042-2020 - 财政年份:2020
- 资助金额:
$ 2.4万 - 项目类别:
Alliance Grants
Towards Efficient Software-Defined Accelerator-Rich Systems
迈向高效的软件定义加速器丰富的系统
- 批准号:
RGPIN-2019-04613 - 财政年份:2019
- 资助金额:
$ 2.4万 - 项目类别:
Discovery Grants Program - Individual
Towards Efficient Software-Defined Accelerator-Rich Systems
迈向高效的软件定义加速器丰富的系统
- 批准号:
DGECR-2019-00120 - 财政年份:2019
- 资助金额:
$ 2.4万 - 项目类别:
Discovery Launch Supplement
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