Towards Efficient Software-Defined Accelerator-Rich Systems

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With the significant slowdown of general-purpose CPU scaling, the computing industry has been actively exploring specialized and programmable hardware accelerators, such as GPUs and FPGAs, to bring orders-of-magnitude performance and energy gains for key applications such as machine learning, computational genomics, and scientific computing. While GPUs have already made a great success in the past decade, recently FPGAs have attracted increasing attention in datacenters: in the past year, Amazon, Alibaba, and Huawei all announced the public access of their FPGA-enabled cloud. However, there are two major challenges that impede the wide adoption of such heterogeneous systems with FPGAs in software applications. First, it is very difficult to program them since traditionally the use of FPGAs has been limited to a small group of hardware experts. Second, it is nontrivial to figure out whether a software application can get better performance on a system with FPGA or its strong competitor GPU. The long-term goal of this project is to enable the wide adoption of heterogeneous systems with FPGA accelerators in the vast software community, by developing efficient programming and runtime support for such systems to provide competitive performance, performance/watt, and/or performance/dollar. First, we will develop a software developer friendly programming framework that achieves efficient end-to-end system performance. To reduce the significant hardware expertise required by existing high-level synthesis (HLS) based accelerator designs, we plan to characterize common HLS programming patterns, automate their code transformation and design space exploration. Instead of focusing on a single accelerator design, we plan to provide system-level compilation and optimization that optimizes the communication between multiple accelerators, their memory system, and the host CPU cores. Second, we will develop an analytical model and program analysis tools to provide early-stage guidance in selecting FPGA or GPU acceleration for a given application. Our first step is to port widely recognized GPU (FPGA) benchmarks to FPGAs (GPUs), and quantitatively compare their performance. Based on the in-depth breakdown analysis, we will build an analytical model, develop program analysis tools and apply machine learning techniques to extract model factors from the application source code to guide the FPGA and GPU selection. The proposed research will develop critical technologies, reusable methodology and tools for efficient software-defined heterogeneous systems, to enable the software industry to continue scaling in post-Moore's law era. It will significantly accelerate the computing efficiency of driver applications that are key to Canada's economy and security, such as machine learning, personalized healthcare, scientific computing, and big data analytics. Moreover, it will provide many research and development opportunities to train our next-generation professionals.