无杂散动态范围（SFDR）是表征DAC线性度最重要的指标，也是高速高精度DAC设计的瓶颈所在。本课题研究电流舵DAC中输出阻抗、输出波形毛刺与输入码字的关系，分析谐波失真产生的原因和对SFDR造成的影响，为提高DAC的高频SFDR提供新的科学方法和设计思路。本课题组首次提出了通过减小正负输出端的阻抗差，可以降低输出阻抗与输入码字的相关性，显著提高DAC 在高频的SFDR 指标，并提出利用新型双对称开关结构和恒定阻抗电流源技术，减小DAC正负输出端阻抗的差别，提高SFDR；另一方面研究相应的数字信号处理算法，结合开关序列优化，设计新型数字校正技术，降低DAC的输出波形毛刺与输入数字码字相关性，减小DAC的谐波失真。根据研究成果，采用65nm先进工艺设计具有高线性度的14-bit 2GS/s DAC进行验证，为克服DAC的SFDR在高频下降的难题提供解决思路。

Spurious-free dynamic range (SFDR) is the most important target in high speed DAC design, and has been the bottleneck of high-speed high-precision DAC. At high frequency, the output impedance and the output waveform glitch has correlation with the input code, and this is the main reason to generate harmonic distortion. This study intends to in-depth research relationships between the input code word SFDR with output impedance and the output waveform, and proposes new method to improve SFDR. Against The output impedance problems, this project researches the improved dual symmetric switch and a new constant output impedance of the current source technology to reduce the difference between the positive and negative DAC output impedance, so the SFDR will be improved; Against the output waveform glitches problem, the project research corresponding digital signal processing algorithms, combined with the switching sequence optimization, design new digital correction techniques, to eliminate the output glitch, to reduce the harmonic distortion of the DAC. To verify the research results achieved, a high linearity 14-bit 2GS / s DAC will be designed.