对集成电路计算能力不断增长的要求促进了14-28nm主流制造工艺以及复杂多核片上系统（MPSoC）架构的出现。在此趋势之下，集成电路的可靠性问题日益严重，导致使用过程中自然、人为失效（故障）频发。因具有“抗使用中失效能力”，片上自主测试-自主修复技术近年来备受关注。然而此技术目前仍存在诸多问题，包括：自身功耗偏高、数据稳定度不足、对人为可靠性失效问题响应能力较差，以及自主调节“副作用”较大等。上述问题阻碍了其与MPSoC实现高度融合。本研究针对以上问题，旨在通过探索多核条件下的自主测试调度技术，结合新型片上自主测试结构设计，并挖掘片上自主修复潜力，攻克高稳定度片上自主测试、多约束条件下测试调度、低损耗片上自主修复等关键技术，实现片上自主测试-自主修复技术与MPSoC的高度融合，促进其抗失效能力的发挥。最终，推进集成电路全生命周期可靠性保障。

Nowadays, high requirement of integrated circuit (IC) performance significantly improves IC integration density, which reduces the manufacture of technology node to 14-28nm, and drives the emergence of complex multi-processor system on chip (MPSoC). As a result, the trends above cause more in-use reliability failures, including deliberate reliability failures. Fortunately, on-chip self-test and self-adaptation technology provides a (and maybe the only) solution to prevent in-use failures，which attracts a lot of attention in recent years. However, issues like high operation power, low data stability, lack of ability to deal with deliberate reliability incident, and non-negligible "side effects" degrade the integrability of this new technique to MPSoC, and reduce the solidity and practicability of this promising solution. In this project, through the investigation of multi-processor self-test scheduling technology, novel high-stability on-chip self-test architectures, and novel on-chip self-adaption solutions, we aim to investigate the critical techniques including high stability self-test, test task scheduling technique in face of multiple constraints, and low-cost on-chip adaption techniques. With the efforts above, we can obtain on-chip self-test and self-adaption system with lower power cost, higher accuracy and efficiency, which will highly increase the integrability of this new technique to current MPSoCs. With this project implemented, we will dramatically improve the lift-time reliability and security of ICs, through enhancing the application of on-chip self-test and self-adaption technique in practice.