使用高压p-LDMOS可以简化高压集成电路设计，提高芯片性能。通常，p-LDMOS的电流密度约为n-LDMOS的1/3到1/2。如果能使p-LDMOS的电流密度媲美n-LDMOS，则芯片成本可以显著地降低且性能将进一步提高。据此，本项目将研究一种额定电流密度和超结n-LDMOS媲美的高压超结p-LDMOS。兼容现有工艺，该项目的超结p-LDMOS将同时使用空穴和电子分别作为多数载流子在各自的半导体区域导电而不形成电导调制效应。因此，该超结p-LDMOS的额定电流密度可以提高约三倍，同时还能保持单极性器件的快速关断。该超结p-LDMOS仍然是一个外加栅压信号直接控制P型沟道的三端器件，其N型沟道则采用全新的基于三维设计的控制理念和方法实现自动控制。因此，在不增加任何栅驱动损耗以及无需任何额外电路和元件的情况下，可实现同一工艺下制作的超结p-LDMOS和超结n-LDMOS额定电流密度的匹配。

By applying high-voltage p-LDMOS in High Voltage Integrated Circuit (HVIC), the circuit design can be simplified and the performances of the chip can be improved. Usually, the current density of p-LDMOS is about one third to one half of that of an n-LDMOS. Therefore, if the current density of p-LDMOS can be improved to match that of an n-LDMOS, the cost of HVIC can be much reduced and the performances can be further improved. In this project, a novel Super-Junction p-LDMOS with its current density comparable with that of a Super-Junction n-LDMOS is investigated. Compatible with present process, the proposed Super-Junction p-LDMOS applies both hole and electron as majority carries to conduct current without conductivity modulation effect. Thus, the current density of the Super-Junction p-LDMOS is improved by about three times and the device maintains its fast turning-off as a unipolar device. The external controlling signal is still applied on the gate of the P-type channel, and the N-type channel is auto-controlled with proposed novel controlling method based on a three-dimensional concept. The current density of the proposed Super-Junction p-LDMOS can be improved to match that of a Super-Junction n-LDMOS implemented through the same process, without increasing any gate-driving power, any extra circuits and components.