Polar码是编码理论界最新的理论突破，具有渐进的最优解码性能，是未来通信与存储应用的强有力竞争者。本研究基于算法和硬件解码器的联合优化来设计符合未来应用需求的polar解码器算法及其对应的解码器硬件架构。本研究首先探索polar码低复杂度的列表解码算法和基于图的迭代解码算法。同时本研究还将设计针对新型polar码的高效解码算法。基于所设计的解码算法，本研究将设计对应的低功耗、高性能的解码器硬件架构。最后，本研究还将设计基于FPGA的polar码解码性能仿真平台。

Polar codes are the latest breakthrough of the coding theory society. The asymptotically optimal performance of polar codes makes them very competitive in future communication and storage applications. Based on the joint decoding algorithm and decoder architecture optimization, this research aims to develop decoding algorithms and corresponding decoder architectures for future applications. First of all, the low complexity list decoding algorithm and graph based iterative decoding algorithm will be studied. The efficient decoding algorithms for newly developed polar codes will also be investigated. Based on the newly developed algorithms, the corresponding low-power high performance decoder architectures will be considered. At last, the FPGA emulation platform for the evaluation of decoding performance will be designed.