面向100Gbps报文处理的硬件加速模型及机理研究

硬件加速是网络设备报文处理性能提升的重要手段，而随着100Gbps高速链路技术的出现和标准化，高速报文处理系统中"存储墙"以及软硬件通信带宽的瓶颈作用进一步凸显，现有硬件加速技术难以匹配上述发展趋势，亟待深入探索和研究，并取得突破。项目提出将报文处理功能卸载与流量卸载加速方法有机融合，对面向100Gbps报文处理的硬件加速模型及运行机理展开研究：通过借鉴并利用软硬件协同设计领域相关理论和方法，构建基于任务序列的报文处理加速模型；利用图论、组合搜索等数学及建模工具，设计软硬件通信开销敏感的任务序列功能卸载加速机制；面向网络流量负载时间局部性开发，提出大流感知的自适应任务序列流量卸载加速机制；基于计数型布鲁姆过滤器技术，设计实现支持快速匹配的、存储空间优化的任务序列Cache。项目研究成果将为构建高性能100Gbps报文处理系统提供新的加速手段，具有重要的理论及实践意义。

Hardware acceleration is an important means to improve the packet processing performance of network equipments. However, with the emergence and standardization of the 100Gbps high-speed link technique, the bottlenecks of "Memory Wall" and the SW/HW communication bandwidth become even worse in packet processing systems. The existing hardware acceleration technologies cannot catch up with the above trends, and it is in urgent need of in-depth study and a breakthrough. The project proposes to integrate the function offloading and the traffic offloading acceleration methods for the research of the hardware acceleration model and mechanism for 100Gbps packet processing: the theories and methods in the field of Hw/Sw codesign are utilized for designing task-trace-based packet processing acceleration model; the traffic offloading acceleration mechanism based on the task traces is studied in consideration of Hw/Sw communication overhead, by using the tools of graph theory and combination searching technology; the heavy-hitters-awared traffic offloading acceleration mechanism for task traces is proposed to exploit the time locality in the network traffic workload; the counting bloom filter technology is adopted for the design and implementation of the memory-optimized task trace cache supporting fast match. The research results of the project will provide a new way for building high-performance 100Gbps packet processing system, and it has important theoretical and practical significance.