众核处理器内部互连规模不断增加给传统片上互连网络带来了严峻挑战，片上光互连技术有效克服了传统金属互连的诸多不足，给更大规模片内互连通信结构提供了一条崭新技术途径。但如何结合片上光互连技术优势，设计适应更多核心互连通信需求的片上光互连网络，仍然面临着高性能、可扩展、低功耗、高适用等方面的严峻挑战。本项目将提出一种面向众核处理器的片上光互连网络体系结构，并深入研究其设计实现关键技术，主要包括：基于全光互连、光电混合互连的高性能可扩展片上光互连网络体系结构；互连结构、网络协议、任务调度、模块单元设计等多个层面的片上光互连网络低功耗设计技术；面向监听协议与目录协议的片上光互连网络缓冲一致性协议优化技术；片上光互连网络性能功耗分析模型及硬件设计资源优化方法等关键技术。本项目研究可为未来我国众核处理器片内互连结构设计和实现提供坚实的理论和技术基础，具有重要的理论与应用价值。

The continual increasing of many cores brings great challenges to the traditional on-chip network. The on-chip nanophotonic technology capitalizing on its rate, capacity, and low energy consumption can overcome many insufficiencies of the traditional metal interconnects and then offers a new ubiquitous solution to the on-chip global transmissions for our future many-core processors. However, to take full advantage of the on-chip nanophotonic technology, the researchers still face some critical challenges in terms of performance, power consumption, scalability and usability when architecting the optical on-chip network for the inter-core communication environment of many-core processors. This project will focus on the design details of the optical on-chip network architecture for many-core processors. The ongoing critical techniques of this project include: the high-performance scalable on-chip network architectures for global optical and hybrid optical-electric interconnects; the low power optimizations towards optical network-on-chips at interconnect structure, network protocol, task scheduling and component design levels; the optical-network based cache coherence optimizations for the snoopy and directory protocols; the highly-efficient hardware design space exploration methodology along with the analytical performance and power consumption models for the optical network-on-chips, and so on. The research of this project can provide the solid theoretical and technical foundations to construct the on-chip interconnect structure for our future many-core processors, and therefore will have its significant application foreground.