布线是FPGA CAD流程中耗时最长的步骤，而现有FPGA布线算法存在效率低的缺点，已经难以适应现代大规模FPGA电路的布线。因此，高效的FPGA布线技术已经成为制约国产高效FPGA CAD软件研发的重要因素。针对此问题，本项目拟研究较优布线解空间预测和线网自适应并行布线关键技术，提出面向现代大规模电路的高效FPGA布线方法，具体包括：(1)研究较优布线解空间预测和轻量化搜索理论，提出线网最优布线路径高效搜索方法；(2)针对布线过程中存在的布线路径重复搜索问题，研究基于历史布线信息的启发式布线路径重用方法；(3)最后，在此基础上引入线网抽象和分解的思想，研究基于线网特征的混合划分方法和线网自适应并行布线策略，提出面向大规模电路的高效并行FPGA布线算法。研究成果能够实现对现代大规模FPGA电路的高效布线，为国产高效FPGA CAD软件的研发提供理论支撑和技术支持。

Routing is the most time-consuming step of the FPGA (Field Programmable Gate Array) CAD (Computer Aided Design) flow. However, the existing FPGA routing algorithms have the shortcomings of low routing efficiency, which are difficult to adapt to the routing of modern large scale FPGA circuits. Therefore, the inefficiency of FPGA routing has become an important factor in restricting the development of the domestic FPGA CAD software. In order to improve the FPGA routing efficiency, this project studies the key technologies of better routing solution space prediction and adaptive parallel routing strategy, and then proposes an efficient FPGA routing approach for modern large scale circuits. The proposed routing approach generally includes the following three parts: (1) based on the theories of better routing solution space prediction and lightweight search method, an efficient optimal routing solution search algorithm is presented; (2) aiming at the problem of repetitive calculation of routing paths during the routing process, we conduct studies on the heuristic routing path reusing method based on the history routing information; (3) at last, with the applications of nets abstracting and decomposing methods, we study the feature-based nets partition approach and adaptive parallel routing strategy, and then present an efficient parallel FPGA routing algorithm oriented to modern large scale circuits. The research results of this project can significantly accelerate the routing of modern large scale FPGA circuits, and provide theoretical and technical supports for the development of domestic efficient FPGA CAD software.