利用铁电材料的负电容特性降低晶体管的亚阈值摆幅是解决当前集成电路功耗与稳定性问题最有前景的途径之一。本项目将系统研究铁电聚合物PVDF薄膜的负电容特性，并开发其在低功耗场效应晶体管中的应用。首先通过采用Langmuir-Blodgett (LB)技术制备不同厚度的纳米尺度的PVDF薄膜，研究PVDF薄膜与电介质层串联结构的电容增强效应，以确定负电容特性的稳定条件；通过研究金属-铁电层-介电层-半导体(MFIS)结构电容的电学性能，建立理论模型揭示负电容特性的产生机理；同时通过设计优化金属-铁电层-介电层-半导体结构场效应晶体管(MFISFET)的器件结构和工作参数，实现基于PVDF薄膜负电容特性场效应晶体管的低电压、低功耗操作。本项目的研究将为有效利用铁电负电容改善集成电路功耗提供一定的理论和技术基础。

Negative capacitance in ferroelectric materials, which can be incorporated into a transistor for lowering the subthreshold swing, provides a promising solution to reduce the power consumption of integrated circuit and to improve the stability of the system on chip. The research proposed here seeks to investigate the negative capacitance effect in ferroelectric polymer PVDF thin films, and to exploit this new effect for low power field-effect transistors. PVDF thin films with different thicknesses in nanometer range will be prepared by Langmuir-Blodgett (LB) technique. Negative capacitance in PVDF can be stabilized in a series capacitance system using an appropriate dielectric layer where the total capacitance is enhanced. The electrical properties of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure will be studied and a theoretical model to describe the mechanism for generating negative capacitance will be established. In order to realize a low voltage and low energy operation in negative capacitance field-effect transistors based on PVDF thin films, the device structures and operating parameters of Metal-Ferroelectric-Insulator-Semiconductor Field Effect Transistor (MFISFET) will be optimized. The achievements in the proposed research will provide necessary theoretical and technical information for improving the power dissipation of electronics using negative capacitance.