随着芯片集成度的不断提高，集成电路测试已成为半导体工业中最大的挑战之一。降低测试成本和测试功耗是近年来集成电路测试领域的研究热点，但目前尚未形成完整的理论体系。本课题拟以基于线性解压器的测试压缩环境为切入点，从测试压缩的基本理论出发，结合低功耗测试技术，建立低成本、低功耗的测试技术体系。主要研究内容如下：首先，充分利用确定性测试集的特点以及基于线性解压器的压缩方法的优势，针对全扫描电路提出测试数据压缩率高、测试功耗低的扫描测试结构；其次，突破传统线性解压器的限制，针对单固定故障和时延故障模型设计新型的线性解压缩结构，进一步降低测试数据量和测试功耗；再次，根据提出的扫描测试结构和线性解压缩结构提出相应的测试产生算法；最后，将这些成果应用到寄存器传输级等高级电路中。本课题的研究将在一定程度上解决超大规模集成电路测试的瓶颈问题，同时为我国在EDA和CAD方面拥有自主知识产权的软件做出贡献。

With the increase of integrity in chips, testing for integrated circuits has become one of the greatest challenges in semiconductor industry. Reducing test cost and test power is a hot research spot in the field of integrated circuit testing in recent years, however there is still no complete theory system. From the basic theory of test compression and low power test technology, this project attempts to put forward the test compression environment based on linear decompression, and establish the testing system of low test cost and low test power. The main research contents in this project are as follow. First, the scan test architecture for full scan design, in which both the test power and the test data are low, is presented, by making full use of the characteristic of deterministic test set and the advantages of test compression scheme based on linear decompression. Second, a kind of new linear decompressor architecture is designed by breaking down traditional one for further decrease of test data volume and test power. Third, the ATPG fitting for the proposed test architectures will be specially designed. Finally, these research results will be applied to advanced circuits such as register-transfer level circuits. Thus, this project will resolve the bottleneck for the testing of VLSI in some degree, and contribute to owning the software with private science product right in EDA and CAD for our country.