功耗自适应视频编码与多核处理器架构优化研究

视频多媒体应用正朝着超高清、3D、多标准方向快速发展，而芯片设计则面临计算量飙升、功耗剧增等瓶颈问题。专用的ASIC芯片在算法的可扩展性、多标准的支持上难以突破，而基于多核的芯片则在体系架构上欠缺针对视频编码算法框架的优化，与ASIC的性能差距较大。本项目旨在基于多核处理器，研究算法、标准可扩展的高能效视频编码方案，主要包括三个部分：1）视频编码算法的软硬件划分和处理器并行映射研究；2）针对视频编码的多核处理器架构优化技术研究；3）功耗自适应的视频编码技术研究。本课题将在多核处理器的软硬件划分机制、视频编码算法的多核映射方法、片上网络架构优化技术、多核处理器资源配置、视频编码能效优化等方面完成关键技术突破，形成基于多核处理器、以应用为导向的软硬件协同设计方法，实现支持算法、标准可扩展的高性能视频编码应用。

Super hi-vision, 3D and multi-standard becoming the hottest topics in multimedia research especially for video coding.Meanwhile, chip design faces bottlenecks which come from huge computational requirement and increased power consumption. For ASIC chip, it's hard to support algorithm extensibility and multi-standard support. For multicore chip, it lacks top level architecture optimization for video coding algorithm framework, and the performance of multicore still much less than ASIC. This project aims to research algorithm & standard extendable,and high energy efficient video coding scheme based on multicore chip.It mainly includes three parts: 1) Software-hardware partition mechanism and multicore parallel mapping for video coding; 2) Top level architecture optimization of multicore processor for video coding; 3) Power adaptive video coding method. This project will achieves many key technologies such as software-hardware partition, algorithom parallel mapping method, NoC (network on chip) optimization, computational resource allocation and energy optimization for video coding. The multicore based, application specific software-hardware codesign methodology can be generalized. Finally, multi-standard supportable, algorithm extendable and high energy efficient video coding can be achieved for next generation video coding chip.