A Combined Deblocking Filter and SAO Hardware Architecture for HEVC
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC
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用于 HEVC 的组合解块滤波器和 SAO 硬件架构
DOI：
10.1109/tmm.2016.2532606
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发表时间：
2016-02
影响因子：
7.3
通讯作者：
Xiaoyang Zeng
中科院分区：
文献类型：
--
作者：
Leilei Huang;Qing Shang;Cong Liu;Xiaoyang Zeng
最新视频编码标准高效视频编码（HEVC）相比H.264/AVC，编码效率提升50%，满足日益增长的视频流、更好的视频质量和更高分辨率的需求。去块滤波器（DF）和样本自适应偏移（SAO）在HEVC编码器中发挥着重要作用，并且SAO是HEVC中新采用的。由于视频编码器的高吞吐量要求，数据依赖性、外部存储器流量和片上存储器区域等设计挑战变得更加关键。为了解决这些问题，我们首先提出了一种基于四分之一LCU的隔行存储器组织，以解决DF的垂直和水平滤波之间的数据依赖性。片上SRAM面积也在四分之一LCU方案的基础上减少至25%左右，且吞吐量没有损失。我们还提出了一种率失真成本计算的简化比特率估计方法，以降低SAO模式决策中的计算复杂度。我们提出的组合 DF 和 SAO 的硬件架构是为 HEVC 帧内编码器设计的，并且所提出的 SAO 的简化比特率估计方法可以应用于帧内编码和帧间编码。因此，我们的设计只需 182 MHz 工作频率即可支持 40 f/s 超高清 7680 × 4320 应用。采用 65 nm CMOS 工艺，总逻辑门数为 103.3 K。
The latest video coding standard high-efficiency video coding (HEVC) provides 50% improvement in coding efficiency compared to H.264/AVC to meet the rising demands for video streaming, better video quality, and higher resolution. The deblocking filter (DF) and sample adaptive offset (SAO) play an important role in the HEVC encoder, and the SAO is newly adopted in HEVC. Due to the high throughput requirement in the video encoder, design challenges such as data dependence, external memory traffic, and on-chip memory area become even more critical. To solve these problems, we first propose an interlacing memory organization on the basis of quarter-LCU to resolve the data dependence between vertical and horizontal filtering of DF. The on-chip SRAM area is also reduced to about 25% on the basis of quarter-LCU scheme without throughput loss. We also propose a simplified bitrate estimation method of rate-distortion cost calculation to reduce the computational complexity in the mode decision of SAO. Our proposed hardware architecture of combined DF and SAO is designed for the HEVC intraencoder, and the proposed simplified bitrate estimation method of SAO can be applied to both intra- and intercoding. As a result, our design can support ultrahigh definition 7680 × 4320 at 40 f/s applications at merely 182 MHz working frequency. Total logic gate count is 103.3 K in 65 nm CMOS process.
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影响因子：
2.5
作者：
S. Kay
通讯作者：
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DOI：
10.1109/tvlsi.2008.2008456
发表时间：
2009-06
影响因子：
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作者：
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DOI：
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发表时间：
2010-12
期刊：
2010 17th IEEE International Conference on Electronics, Circuits and Systems
影响因子：
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作者：
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通讯作者：
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DOI：
10.1109/tcsvt.2012.2221255
发表时间：
2012-12-01
影响因子：
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作者：
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通讯作者：
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