纳米时代，MOSFET越来越接近其物理极限，采用新原理、新器件以替代MOSFET成为了必然。基于隧穿原理的TFET具有良好亚阈摆幅和静态功耗，是有效候选器件之一。然而，由于Si TFET隧穿几率低、隧穿面积小、载流子迁移率损失严重，其开态电流远低于MOSFET的开态电流，是制约其发展的关键瓶颈。为解决Si TFET所面临的问题，本项目拟基于Si基应变材料、开展多子沟道TFET基础理论与技术研究。该器件创新的采用多数载流子形成沟道并利用Si基应变材料形成“L”型隧穿面，其载流子迁移率高、隧穿几率与隧穿面积大，可极大提升Si TFET的开态电流。本项目将重点探索Si基应变多子沟道TFET形成机理与工作机制，研究其开关电流比优化方法，建立器件结构模型，分析其阈值电压、开/关态电流、亚阈摆幅等电学特性随关键物理参数的变化规律，开发器件工艺，制备器件样品，为Si基TFET在纳米芯片中的应用奠定基础。

As MOSFET scaling has attained the nano scale, alternative concepts are intensively being investigated. The Tunnel-FET (TFET) transistor, compatible with CMOS technology but with a different operating principle (tunneling conduction mechanism), appears as a promising solution to replace the conventional MOSFET. Unlike MOSFET, the ON current of TFET is not only limited by the electron transport but also by the electron injection due to band to band tunneling, so TFET presents better short channel effect and a subthreshold swing lower than 60mV/dec, reducing the power dissipation. However, owing to 1.12eV band gap of Si material and minority carriers in the thin inversion layer, the tunneling probability, tunneling area and carrier mobility of Si TFET are low, making the ON current of Si TFET only in the range of 0.1-10μA/μm, much less than the ON current level of MOSFET.To boost the ON current of Si TFET, this project will design a new type of TFET, using the majority carriers of semiconductor as conductive channel. Owing to the much narrower band gap and higher carrier mobility, Si-based strained materials are chosen for the new TFET. Thus, a L-type tunnel line will be easily to obtained, enlarging the tunneling region greatly. The suppressing structure of OFF current will also be studied. With the help of ideas above, the performance of Si-based TFET will be improved greatly. The influence of interface state and traps on I-V, C-V characteristics will be discussed and the model of threshold voltage, ON current, OFF current, etc, will be established. Finally, the preparation of the device samples will be carried out, to indicate the validity of our design. This project can provide valuable foundation for the application of Si-based TFET in nano chips.