锁相环电路 (PLL) 在芯片系统的射频、数字、模拟等各模块中发挥着不可替代的作用。近年来随着集成电路制造工艺的持续进步，经典的PLL设计技术在实现低功耗、高能效时遭遇到了前所未有的挑战：模拟PLL存在着电压裕度过低、器件匹配误差较大等问题，需要消耗大量的功耗来进行改善；数字PLL在数字量化的过程中存在的误差问题，对频率调制的精度、相噪等性能造成了严重的影响，需在精度、功耗、面积、范围中做出权衡。.本项目拟对限制PLL能效的各种因素进行深入分析，探索提升能效的机制，突破传统PLL设计技术在先进工艺下的局限性并研究解决精度、功耗等关键问题。结合模拟电路精度与数字电路功耗的优势，提出新型数模混合PI控制PLL结构，模拟辅助数字鉴相器技术、偏置电压频率调制技术等。通过对结构和电路技术的组合创新，设计实现低功耗、高能效的PLL芯片，对通信、物联网、高速接口等领域的发展有着重要的科学意义和经济价值。

Phase-Locked Loop (PLL) plays an irreplaceable role in each sub-block of system on chip. In recent years, the classic PLL design techniques have suffered great challenges from the advanced integrated circuit (IC) technology down scaling: (1) analog PLL exists limited voltage headroom, transistor mismatch problem, which needs to consume large amount of power to compensate; (2) digital PLL brings additional quantization error to degrade the frequency accuracy and phase noise. It faces the tradeoff among accuracy, power, area and dynamic range. .The proposed research is to make a comprehensive study on the issues that limit the energy efficiency of PLL in advanced IC technology, exploring the mechanism that can improve the energy efficiency, proposing the new type of hybrid PLL architecture, analog-assisted digital phase detector, biasing-voltage frequency tuning scheme. Via the innovation by architecture and building blocks, realizing a low-power, highly energy-efficient PLL chip design. This research has significant scientific and economic value in the development of wireless communication, internet of things, high-speed interface and many other applications.