硬件安全保障着国计民生的各个领域。硬件安全系统需要同时满足传统的性能指标和额外的安全指标，而两类指标的设计实现方向往往是相互矛盾的，设计硬件安全系统具有非常大的挑战。安全计算设备的体系结构的每一层的安全都建立在对下一层的信任上，系统最底层是由可信根组成。纯粹软件层面的安全解决方案并不存在，因为软件解决方案一般都会被低于其的底层攻击所绕过。因此信任根往往都是基于底层硬件实现的，而真随机数发生器是硬件可信根的不可或缺的主要组成模块。软件定义芯片是当今计算机系统研究中的热点。与通用处理器及专用芯片不同，软件定义在保持高度灵活性的同时还具有较高的能量效率。本课题着重解决如何在软件定义芯片中设计安全、可靠有效和可验证的硬件真随机数发生器。本项目的意义在于充分结合软件定义芯片的特点，研究该平台上物理真随机数发生器的设计方法学，提高软件定义芯片真随机数发生器的稳定性和实用性

Hardware security ensures various aspects of the national economy and people's livelihood. A hardware security system should meet the requirements of both the conventional performance and additional security metrics. However, designs and implementations toward these two design targets are usually contradicted one another, which brings a great challenge for engineers. Every layer of the architecture of the modern security computing system relies on the trust of the layer below. The physical root-of-trust lays the foundation of such an upside-down pyramid. Software-only security solution doesn’t exist, since protection method at the software-level could be easily by-passed via attacks from a level below. If we traced down to the very bottom, physical root-of-trust, such as TRNG (True Random Number Generator), provides the origins of the security. The SDC (Software Defined Chip) is a recent research hotspot for its advantages on both flexibility and efficiency. This research will focus on how to design secure, robust, and verifiable physical TRNG for SDC. The special design rationales for applications on SDC will be analyzed and used to develop a specific design methodology of TRNG for SDC.