随着物联网和人工智能飞速发展与融合，在边缘端实现智能处理，已成为“万物智联”的迫切需求，可极大地拓展物联网应用的边界，带动新一轮的信息技术变革。如何将人工智能算法轻量化并高效地部署在资源受限的边缘计算平台，仍是个亟待解决的关键科学问题。本项目着力于解决存储资源受限下的边缘智能处理问题，通过软硬件协同设计，目标实现存储能效>1.3TOPS/MByte的深度学习加速器。软件层面，本项目将研究一种基于混合对数（2和根号2）的训练后量化方法，不依赖校正数据集，在模型准确率损失<3%的条件下，实现>8倍的模型压缩；硬件层面，本项目将定制设计混合对数量化专用计算单元，研究有限状态机与序列映射表相结合的控制逻辑架构，并在FPGA平台完成专用加速器的设计和验证，通过对多层级缓存结构和数据流计算阵列的细粒度控制，优化平均数据复用率至10倍以上，提升阵列和片上存储利用率至>90%，降低控制逻辑开销至<1%。

With the rapid development and integration of the Internet of Things and Artificial Intelligence, intelligent processing at the edge has become an urgent need for "Internet of Intelligent Things”, which can greatly expand the boundaries of the Internet of Things applications and drive a new round of information technology revolution. How to efficiently deploy lightweight artificial intelligence algorithms on resource-constrained edge computing platforms is still a key scientific problem to be solved. This project focuses on solving the problem of edge intelligent processing under limited storage resources. Through the collaborative design of software and hardware, the goal of the project is to design a deep learning accelerator with storage energy efficiency > 1.3TOPS / MByte. At the software level, this project will study a post-training quantization method based on a mixed-base (2 and root number 2) logarithm, which does not rely on data set for calibration, and compress the model by > 8 times with the model accuracy loss of <3%; at the hardware level, this project will design a dedicated computing unit for mixed-base logarithmic quantization, study the control logic architecture based on the combination of finite state machine and sequence mapping table, and completes the design and verification of the dedicated accelerator on the FPGA platform. The fine-grained control of multi-level memory hierarchy and PE array optimizes the average data reuse rate to more than 10 times, improves on-chip storage and PE array utilization to > 90%, and reduces the control logic overhead to <1%.