随着我国IC产业的高速发展，混合信号电路的量产测试成为了制约产业发展的主要技术瓶颈之一。CP-PLL作为大多数电子系统中关键的混合信号电路模块，其量产质量和测试成本对电子产品的上市时间、生产成本以及性能稳定性具有重要影响。然而现有的CP-PLL测试方案存在着测试成本高，可靠性低的问题，难以满足当前大规模工程量产测试需求。为了解决这个问题，本项目在定性定量的分析CP-PLL的结构故障对其性能影响的基础上，提出了低成本融合结构测试与性能评估的CP-PLL可测性方法，并设计了基于自参考时间数字转换器的高可靠性CP-PLL片上可测性电路。实现通过一个片上可测性电路分时完成CP-PLL的全数字片上故障探测和高分辨率片上抖动测量。预期实现故障覆盖率大于98%，抖动测量分辨率小于1ps，并降低测试电路的复杂度和测试成本，提高测试可靠性。

With the rapid development of IC industry in China, the mass production test of mixed-signal circuit has become one of the main technical bottlenecks restricting the industrial development. The charge-pump phase-locked loop (CP-PLL), which is a key mixed signal circuit module in most electronic systems, its production quality and test cost have a big influence on the time to market, the production cost and performance stability of electronic products. However, the existing test methods of CP-PLL have the problems of high test cost and low reliability, which makes it difficult to meet the current mass production test requirements. To solve the problem, based on the qualitative and quantitative analysis of the influence of faults in the structure of CP-PLL on its performance, this project proposes a method integrated structural test and performance evaluation at low cost. And the design-for-testability structure of CP-PLL with high reliability based on self-reference TDC is designed. The all-digital fault detection and high resolution jitter measurement of CP-PLL on-chip are completed by a time-sharing design-for-testability circuit. The expected fault coverage is more than 98% and the jitter measurement resolution is less than 1ps. It will reduce the complexity of test circuit and the test cost. The test reliability is also improved.