相比于芯片级ESD冲击，系统级ESD冲击除了会造成集成电路发生更为严重的物理性损伤，还会造成瞬态闩锁、软错误等功能性失效，对片上ESD保护电路提出了更为苛刻的设计要求。与此同时，纳米尺度集成电路特征尺寸缩小带来的ESD设计窗口不断变窄的问题也增加了高可靠性ESD设计的难度。采用片上和片外ESD保护网络协同设计的“系统级有效的ESD设计（SEED）”方法是解决这一难题的有效途径。本项目重点解决面向SEED方法的模型模拟、测试表征和协同设计三个方面的难题，包括：建立ESD测试激励源、片外和片上ESD保护网络等三部分的SPICE模型并实现电路级仿真；设计面向SEED的高性能电源钳位保护电路，建立ESD钳位电路瞬态特性的测试表征方法；提供高ESD鲁棒性的片上/片外ESD协同设计方案，避免物理性失效的同时，有很好的TLU和软错误免疫性。

Compared component-level electrostatic discharge (ESD) stress, system-level ESD stress can induce harsh physics failures and additional functional failures at integrated circuit (IC) pins. The ESD-induced functional failures include transient latchup (TLU) and soft error. Moreover, with the IC technologies entering the nanometer range, the ESD design window began to get narrow as much thinner gate oxides and thinner metal interconnects. Hence, we have to face the difficulty to provide high ESD-robustness products in both system-level and component-level. A novel co-design approach of on-chip and off-chip ESD protection is most efficient and cost-optimized, named system-level efficient ESD design (SEED). In this project, improved SEED issues in nanometer scales will be investigated, including modelling, simulating, testing, and circuit strategy. The whole SPICE models will be built, including lumped model of ESD test generator, high-order model of off-chip discrete ESD device, and compact model of on-chip ESD circuit. Then, the high robustness ESD power clamp will be designed. And the power-off and power-on transient performance of power-rail ESD clamp circuit will be investigated. Finally, a high-ESD-robustness co-design approach will be provided, considering both physics failure and functional failure immunity.