超低压传感器接口IA-ADC协同设计技术研究
结题报告
批准号:
61904027
项目类别:
青年科学基金项目
资助金额:
23.0 万元
负责人:
周雄
依托单位:
学科分类:
F0402.集成电路设计
结题年份:
2022
批准年份:
2019
项目状态:
已结题
项目参与者:
--
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中文摘要
物联网、可穿戴设备、植入式医疗电子等新兴技术迫切需求微型尺寸、自主供能、长使用寿命的无线传感器接口SoC。能量采集是该类SoC 实现自主供能的可行技术手段。但因能量采集低能量密度和低输出电压的特点,为了最优能效,此类 SoC需要同时在超低功耗和超低电压的双重约束下设计。通常,模拟采集前端由仪表放大器(IA)和模数转换器(ADC)以开环的方式构成。在多数设计中,目前对两个模块在性能提升和功耗降低方面是独立进行的,未能达到最优的系统性能和能效。此外,在开环结构下,低电压模拟电路还存在有限的电压摆幅,较差的线性度以及较低的动态范围等问题。申请人拟提出通过结合IA和ADC领域的多种低功耗技术,实现IA-ADC的协同设计。同时,闭环系统可有效解决低电压设计面临的挑战。通过底层电路单元,电路模块以及系统架构的研究、分析和设计,该项目有望提出新型低功耗技术,突破目前同类设计的能效水平。
英文摘要
Emerging techniques like internet-of-things (IoT), wearable healthcare devices as well as implantable electronics call for millimeter-scale, self-powered, long-lifetime wireless sensor system-on-chip (SoC). Energy harvesting is a viable solution for truly realizing self-power in such kinds of SoC in the coming future. However, harvested energy has characteristics of limited amount of power (nW/mm3~μW/cm3) and ultralow output voltage (<0.5V). Therefore, with consideration of system efficiency, the SoC should be designed under constraints of both ultralow power dissipation and ultralow voltage. ..Micro-signal acquisition analog frontends (AFEs) are always necessitated in massive sensor interfaces. They are typically built with instrumentation amplifiers (IAs) and analog-to-digital converters (ADCs) in an open-loop manner. Usually power reduction and performance optimization are conducted separately in individual block. Moreover, low-voltage analog circuits suffer from limited voltage headroom, poor linearity and thereby constrained dynamic range. .In this project, closed-loop approach for co-design of IA and ADC as one block is proposed for significantly improving the energy efficiency, by taking fully advantage of hybrid low-power techniques from fields of IAs and ADCs. Meanwhile challenges from low-voltage operation will be addressed in a systematic way. The oversampling IA-ADC hopefully can achieve good performance and superior energy efficiency concurrently. As a result, the applicant will design an ultralow-power and ultralow voltage acquisition analog frontend with high dynamic range, low input referred noise as well as high energy-efficient for monitoring physiological signals.
可穿戴设备、物联网、植入式医疗电子对于低功耗、低电压的信号采集前端有迫切的需求。传统的信号采集前端是基于全模拟的设计,没有和后端的模数转换器协同设计,导致在性能和能效层面并不优化。该项目提出了IA-ADC协同设计的方法,将模数转换器的设计技术引入仪表放大器的设计当中,修正了因为制造工艺当中电容失配导致的共模抑制比的损失。该项目完成了两个设计,分别提出了基于数字化的逐次渐进电容修调技术(Successive-approximation capacitor trimming)技术和共模复制技术(common-mode replication)技术,有效地提高了电容耦合仪表放大器的共模抑制比。并且通过底层低功耗电路技术,实现了较低的功耗和较高的能效因子。该项目完成了建模验证、电路与系统的仿真设计、版图实现、流片、封装测试和论文撰写,并发表了集成电路领域的顶会ISSCC和顶刊JSSC论文。培养了多名硕士研究生和博士研究生。该项目提出的技术突破了传统设计技术理论上的的性能极限,有效地提高该类模拟前端的关键指标。该技术在可穿戴生理电信号采集以及仪表类模拟前端中,具有较好的应用前景,可较为简洁地解决微弱信号采集的固有问题。
期刊论文列表
专著列表
科研奖励列表
会议论文列表
专利列表
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation- Based Capacitor Trimming
使用斩波伪电阻器和基于逐次逼近的电容器微调在 50 Hz 下实现 110 dB CMRR 的交流耦合仪表放大器
DOI:--
发表时间:2022
期刊:JOURNAL OF SOLID-STATE CIRCUITS
影响因子:--
作者:张三峰;周雄;高晨;李强
通讯作者:李强
国内基金
海外基金