高速高性能数模转换器（DAC）广泛应用于各类宽带通信系统中，是系统中的核心部件。随着DAC采样率的提升，延迟偏差已经成为限制DAC动态性能的瓶颈，而相关领域的研究还较为薄弱。本研究将从实际DAC电路中的延迟分布特征入手，分析延迟偏差与动态性能的关联性，建立行为级仿真模型，为高性能高速DAC芯片设计提供科学依据。在此基础上，本研究将开展DAC版图优化方法研究，结合层次化优化的思想，探求在不增加功耗的前提下降低延迟偏差的影响的方法。本研究首次提出了一套延迟偏差检测和后台自校正系统，用于检测电流开关单元之间细微的延迟偏差并相应的调整，减小或消除偏差。最终上述技术将应用于高速DAC设计中，实现高性能4GSps 12位DAC。

High-speed digital to analog converters (DAC), which are used in broadband communications, systems, are key components to these systems. With the increasing of DAC sampling rate, delay difference has become a bottleneck limiting DAC dynamic performance. Research in related fields is relatively rare. This research starting from analyzing the distribution of delay difference, will find out the relationship between delay differences to dynamic performance, provide a scientific basis for the design of high-performance high-speed DAC chip. On this basis, this study will conduct layout optimization methods research, exploring ways to decrease the impact of delay variation without increasing power consumption, using hierarchical design method. Meanwhile, the study also put forward a set of innovative delay difference detection and correction circuit for detecting subtle delay deviation and adjusted accordingly. Finally the above technique is applied to the design of the circuit to achieve a high performance 4GSps 12-bit DAC.