集成电路已进入甚大规模，随着器件尺寸的不断缩短，尤其是在未来几年尺寸缩小到亚10纳米之后，对沟道原子掺杂数的控制精度需达个位以避免性能大幅度波动，同时掺杂原子的电子在数个纳米尺度内会呈现局域化现象，这都限制了源漏和沟道之间突变结的形成。而近年来出现的源漏和沟道掺杂浓度、类型一致的无结FinFET器件由于具有良好的亚阈值特性和短沟道效应抑制能力，未来很可能被工业界所采用而成为集成电路基本单元器件。由于无结器件有效沟道长度受栅极电压调控，尤其当器件尺寸减小到10纳米以下后，有效沟道长度的变化将非常明显，这不仅对传统的输运产生很大影响，对量子输运的影响也不可忽略。本项目将针对该量子输运问题如弹道输运和散射等开发对器件特性影响的SPICE电学模型，为亚10nm无结器件走向工业化打下基础。

The dimension of the transistor will be scaled down to sub-10 nm in a few years and the channel dopant needs precise control in the level of few atoms. Meanwhile electrons localization phenomenon of dopant atoms is observed in a few nanometers scale, which limit the formation of P-N junction between the source and drain. While in recent years, the junctionless transistor with uniform doping in the source, drain and channel, due to good subthreshold characteristics and good suppression on short channel effects, is very likely to be used in mainstream.technology in future. As the effective channel length of junctionless transistor is controlled by the gate voltage, the variation of the effective channel length will be very significant when the device size is less than 10nm. It has great impact on both traditional transport and the quantum transport. This project focuses on developing a SPICE model for the quantum transport including the ballistic transport effect and transport scattering effect for sub 10nm junctionless device for the first time to make it possible to design and evaluate sub 10nm junctionless circuits at early stage.