超大规模集成电路失效率分析方法研究

The advance of integrated circuit (IC) technology brings about significant process variations, making robust circuit design a grand challenge. For instance, in order to achieve sufficiently high yield of an advanced microprocessor containing millions or even billions of replicated cells (e.g., SRAM bit-cells, flip-flops, etc.), the failure rate of each single cell (i.e., cell-level failure rate) must be extremely small. Even though the cell-level rare failure rate estimation has been extensively studied, it remains an open question how we could efficiently estimate the rare failure rate for a circuit (i.e., circuit-level failure rate) or an entire system (i.e., system-level failure rate) containing a large number of cells. This is an extremely difficult problem because of several reasons, e.g., the complicated correlations among cell-level failures, the high dimensionality and the increasing number of PVT (Process, Voltage and Temperature) corners. To address these challenges, in this project, we propose to develop circuit-level and system-level rare failure rate analysis scheme. This scheme includes three parts: (1) the asymptotic approximation of the circuit-level failure rate upper bound by using a linear combination of several sub-circuit failure probabilities with different orders (i.e., concerning about the failure events of different number of cells), and nonlinear modeling method for the failure rate of the entire circuit by solving a set of nonlinear equations; (2) the efficient correlated Bayesian fusion method for the estimation of circuit-level failure rates over different PVT corners; (3) system-level failure analysis prototype by integrating the proposed circuit-level failure rate estimation method into Cacti (i.e., an integrated cache and memory access time, cycle time, area, leakage, and dynamic power model developed by HP Lab.) and micro-architecture simulation environment.

随着半导体工艺进入纳米量级，工艺偏差对电路性能的影响日益严重。尤其是包含大量重复单元的大规模电路系统，必须具有极低的单元失效率，才能够保证全系统具有较高的成品率。尽管国际上已经提出了一系列失效率预估方法，但都集中于对单元电路的分析，在电路级或系统级方面的失效分析工作仍然十分有限。本项目拟考虑特定电路结构等导致的单元失效相关性、多工艺角等对电路及系统性能的影响，研究高维空间多工艺角的高效电路级失效率预估方法，并将其集成到微处理器系统仿真平台，建立系统级失效分析工具原型。主要内容包括：(1)基于子电路失效率，构造用于逼近电路失效率及其上限的线性模型和非线性解析模型；(2)基于不同工艺角系统性能的“相似性”，引入模型系数协方差矩阵等先验信息，来降低电路失效率的预估成本；(3)将电路失效率估计方法集成到存储器仿真工具Cacti和微处理器系统仿真平台，研发较为完整的系统失效分析工具原型。

近年来，随着集成电路特征尺寸的不断缩小和集成度的不断提高，工艺偏差对电路性能的影响日益严重，造成严重的成品率问题。针对由此造成的大规模集成电路超低成品率估计问题，本项目利用电路中不同单元失效事件的相关性，提出了一系列快速预估方法，取得了若干具有国际领先和先进水平的研究成果，如线性方法APA、非线性方法APE、针对截断高斯分布的失效率估计方法T-SSS和基于前端设计和后端设计相关性的成品率估计方法等，以及多PVT条件下的性能分析方法CBMF、超低失效率估计方法CBI、BIBD和BIBC等。此外，本项目还扩展研究了器件级工艺偏差参数提取和考虑工艺偏差影响下的模拟电路建模和优化工作，包括可调模拟/射频电路的硅后调节方法、用于宽带VCO优化的迭代方法、用于降低软错误问题的可靠性优化方法，以及用于电路模块性能可行域边界建模的多目标优化方法等，为下一步进行成品率优化奠定了一定的基础。上述工作以第一作者/通信作者发表期刊论文9篇（包括在EDA领域最有影响力的国际SCI期刊IEEE TCAD发表论文8篇），会议论文4篇（包括在EDA领域最有影响力的国际会议DAC和ICCAD各发表论文1篇）。部分研究成果已在华大九天、珂晶达等相关企业进行推广应用。

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