本项目将基于纳米级标准CMOS工艺，对优化高速中等精度逐次逼近型模数转换器（SAR ADC）转换速度、功耗、复杂度的关键技术进行系统研究。研究Multi-bit/cycle SAR ADC电路复杂度、功耗的优化方法和理论，从而大幅减少所需电容型DAC数量和比较器数量，实现更小的功耗和更低的电路复杂度；研究DAC一体化技术，从而减小ADC输入寄生电容并消除静态功耗；研究比较器速度、噪声性能提升技术，实现更高的SAR ADC速度和精度；研究栅压自举开关的采样速度提升技术，突破开关采样速度对SAR ADC速度的制约；研究比较器时钟边沿位置对SAR ADC速度的影响，探索边沿位置可编程时钟产生器的设计实现方法，实现对SAR ADC速度的优化。通过系统的研究和探索，最终研制高速中等精度SAR ADC芯片样品，为高速中等精度SAR ADC工程化提供理论依据与技术参考。

This project studies the key design techniques for high-speed medium-resolution successive-approximation-register analog-to-digital converter (SAR ADC), based on the nanometer standard CMOS technology. Study will be performed on the optimization method and theory for reducing both the circuit complexity and power consumption of multi-bit/cycle SAR ADC, through greatly reducing the number of capacitive DACs and comparators; study will be done on the DAC merging technique, which is helpful for reducing ADC input capacitance and avoiding static power; study will be performed on the comparator acceleration technique and noise reduction technique, which leads to higher sampling rate and higher resolution of SAR ADC; study will be done on the acceleration technique of bootstrapped switch, in order to overcome the limited speed of traditional bootstrapped switches; study will be performed on the relationship between comparator clock transition position and SAR ADC speed, and the way to realize reconfigurable clock generator will also be explored for transition position programmability in order to optimize the SAR ADC speed. Finally, the SAR ADC will be fabricated and measured, so that these techniques can provide guidance for company engineers.