芯片集成度的不断提高和日益增加的设计复杂性给当前超大规模集成电路（VLSI）布局问题带来许多的额外约束及巨大的求解困难。针对已有研究主要集中在单倍行高电路布局，本项目研究先进制程技术下的VLSI混合高单元布局问题。本项目拟采用最精确计算总线长的1范数线长模型作为目标函数，通过构造函数来准确刻画多倍高单元的电压线对齐约束，利用有解析解的电场能模型快速解决单元散开和栅栏约束问题，从而建立混合高全局布局新模型，并设计基于邻近点交替方向法的算法来高效求解该模型。接着，本项目建立以移动量驱动且考虑宏模块的合法化模型，设计基于模迭代的合法化算法和基于最短哈密顿路的详细布局来提高布局质量。基于上述研究，本项目进一步考虑可布通性、相邻扩散效应和引脚可接入性等约束的混合高单元布局问题。本项目的研究将提出混合高单元布局的新模型和新算法，并最终形成一套效果好、可扩展性高并可高效处理单元个数达到千万级的布局工具。

The increasing chip integration level and design complexity have brought a lot of additional constraints and great difficulties to the current very large scale integration (VLSI) placement problems. Existing researches mainly focus on the single-row-height standard cell placement problems. In this project, we will consider the VLSI mixed-cell-height placement problems with various advanced technology constraints. We will use the l1-norm wirelength function ( the most accurately to calculate total wirelength) as the objective function, and construct a continuous function to characterize the VDD/VSS constraints. Moreover, we will adopt the analytical solution of the electric field energy model to quickly solve the cell spreading and the fence region constraints problem, and finally build a new mathematical model for mixed-cell-height global placement. In order to solve the proposed placement model efficiently, we will develop a novel global placement algorithm based on the alternating direction method of multipliers. Then, we will establish a legalization model which is driven by the cell movement and considers the macros, and design a legalization algorithm based on the modulus-based matrix splitting iteration method and a detailed placement algorithm based on the shortest Hamiltonian to improve the placement quality. Finally, using the mixed-cell-height placement algorithms developed in this project as engine, we will solve the placement problems with different advanced technology constraints, such as routability, neighboring diffusion effect, and pin accessibility. The outcomes of this project will present not only the new mathematical models and novel effective and efficient algorithms for modern mixed-cell-height placement, but also will develop a robust and extendible VLSI placement tool that can handle the mixed-cell-height placement problems with tens of millions of cells.