电路容错设计是当前各类重要电子系统研究中难以回避的问题。传统的电路容错技术的有效性对故障分布具有很强的依赖性。如果故障分布未知，则传统的容错技术难以凑效，甚至无法处理。负相关演化容错是一种以负相关集成为基本思想、以演化计算为设计技术的新型的电路容错方法，具有对未知电路故障进行容错设计的能力。本项目研究负相关演化容错的电路设计规模问题，拓展负相关演化容错模型的设计能力，以胜任更大规模的电路容错设计要求；研究负相关演化容错的工作机制，探索负相关演化容错模型中电路结构变化、电路功能变化以及电路容错能力在其可变化空间的趋向之间的行为关系，以获得对负相关演化容错方法的定性认识，为深入研究和合理应用负相关演化容错方法奠定理论依据。本项目的研究对电路故障容错机理和方法应用具有十分重要的科学意义和实际应用价值。

Circuit fault-tolerance design is an unavoidable issure in most important electronic systems. The technique used by traditional fault-tolerance design methods has strong dependence to the distribution of fault. However, if the distrubtion of fault is unknown, the traditional fault-tolerance design methods will be hard to act, even be invalid. Evolutionary negatively-correlated fault-tolerance is a novel method which is based on the idea of negatively-correlated integration and the using of evolutionry computation. It has the design ability versus unknown fault. This project focus on the scalability of evolutionary negatively-correlated fault-tolerance method, aims at expanding the design ability to catch up with the design requirements on more larager circuits; This project also focus on the study of the mechanism of evolutionary negatively-correlated fault-tolerance. The goal is to explore the behaviour relationship between the changed circuits, the circuits metergasis,and the fault-tolerance ability to gain determine knowledges and achieve theoretical evidences for further study and reasonable applications. This project is with the fundamental scientific significance and practical value of application in the study of circuit fault-tolerance mechanism and method applying respectively.