)芯片特征尺寸小于65 纳米后，NBTI (Negative Bias Temperature Instability) 效应成为纳米CMOS电路可靠性中的关键问题。本项目根据申请人和课题组现在已有科研基础，提出研究65-32 纳米尺度下 CMOS 集成电路NBTI 效应的统计性分析、建模与面向增强芯片可靠性的优化方案，具体包括CMOS 晶体管级的统计性延迟退化模型，CMOS 门级的统计性延迟退化模型，CMOS 电路级的统计性延迟退化模型，基于上述模型的统计性静态时序分析算法与流程、以及与面向统计性波动的电路可靠性增强方案。本项目的开展为准确估计后65 纳米CMOS 电路的延迟退化奠定坚实的理论模型与算法基础，为降低传统芯片可靠性增强方案（譬如Guardband）带来的overhead（譬如面积与功耗增加）指明方向。

When the size of chip feature is smaller than 65 nm,the effect of NBTI (Negative Bias Temperature Instability) becomes a crucial problem in reliability. The project based on existed foundation, make a research on NBTI effect of CMOS integrated circuit at 65-32 nm,whose statistical analysis, modeling and plan of enhancing reliability of the chip, including CMOS transistor-level statistical delay degradation model, CMOS gate-level statistical delay degradation model, CMOS circuit-level statistical delay degradation model, the algorithms and process of the statistical timing analysis and the volatility of the circuit for statistical reliability enhancement scheme,both of them based on above models. The development of the program lays the solid foundation of theoretical model and algorithm for accurately estimate the delay and the degradation of 65 sub-nanometer CMOS circuit, shows the direction of reducing overhead (like area and power consumption increase) which are brought by the traditional chip reliability enhancement program (like Guardband).