近年来半导体产业持续高速发展并对集成电路的最小特征尺寸进行缩小。然而随着每一代关键技术节点中特征尺寸的持续缩小，先进制程研发面临的挑战已经逐渐由传统的光刻主导向光刻与材料工程主导转变，虽然近期极紫外光（EUV）的发展可以缓解光刻本身面临的挑战但并不能扭转这一趋势。作为先进制程核心的光刻、刻蚀和原子层沉积已经突破了传统模组的界限，各自的性能越来越影响到其他工艺的质量。因此为了满足先进技术节点需求，迫切需要建立一种结合光刻和刻蚀工艺、原子层沉积的工艺仿真模型，结合计算光刻的实际，达到提高超大规模集成电路制造领域掩模版图的优化效果。本课题开展的图形化工艺仿真模型的研究可以规避在缺少充分仿真设计分析情况下的硬件设计风险，为先进光刻系统中工艺参数、刻蚀参数、原子层沉积参数菜单的研发提供一定的技术支撑，对缩短研发周期、降低研发成本具有重要的作用，具有重要的理论研究意义和实际应用价值。

The semiconductor has experienced explosion in recent years and has successfully achieved continuous critical-dimension (CD) scaling. However along with the scaling of each new technology node, the development challenges has gradually drifted from the conventional lithography dominating situation to more litho/material engineering dominating. Being the most critical modules of the full process flow, lithography, etch as well as atomic layer deposition (ALD) has broken through the traditional barriers between modules, rather their individual performance has been able to impact their upstream or downstream process. To meet the requirements of the novel technology node development, it is desired that a model could combine the ALD and etching process with the existing lithography modeling manners, to achieve the layout optimization. This project proposes a visualized process simulation model to avoid the hardware design risks when lacking sufficient design simulation ability, and provide support to the parameter characterization in litho, etch and ALD. This proposal will be greatly useful to reduce the research cycle time and lower the cost, and demonstrate its significant theoretical and practical value.