根据摩尔定律，晶体管集成密度约每两年翻一番。高集成度使得功耗成为片上多核系统设计人员面临的一大挑战。通过三维集成技术将STT-MRAM与处理器集成在一起，可以大大降低静态功耗。然而，STT-MRAM的写操作是一个费时且耗能的过程，因此基于STT-RAM的片上缓存架构设计需要新的低功耗设计技术降低动态功耗。本项目主要研究基于STT-RAM的片上缓存的低功耗设计技术，降低动态功耗。首先，利用STT-MRAM写能耗和温度的依赖关系，提出利用片上温差的三维多核处理器STT-MRAM缓存写能耗优化技术。然后，分别从温度、工艺偏差和数据访问属性的角度出发提出了新的数据刷新技术用以降低小尺寸STT-MRAM的刷新能耗。最后，利用新兴的Multi-level STT-MRAM存储单元搭建三维片上多核系统的缓存,提出了一种根据所运行的应用动态切换存储模式的自适应配置技术，降低访存能耗并提升访存性能。

As predicted by Moore's law, transistor integration density doubles approximately every two years. High integration density makes power consumption a big challenge for MPSoC designers. By stacking STT-MRAM atop processor layer through 3D integration, leakage power can be reduced dramatically. However, STT-MRAM writing is a power and time consuming procedure。 Therefore, STT-MRAM based on-chip cache design requires novel low power design techniques to reduce dynamic power consumption. In this proposal, we explore the low power design opportunities for STT-MRAM based cache hierarchy of 3D MPSoCs. Firstly, we take advantage of STT-MRAM write energy's dependency on temperature, and propose thermal-aware write energy optimization. Then, we propose several novel refresh techniques from thermal, process variation and data access property perspectives to save dynamic power incurred by small STT-MRAM storage cell refreshing. At last, we exploit the emerging multi-level STT-MRAM cell to build the cache hierarchy of 3D MPSoCs. We propose an adaptive configuration technique to switch storage cell between 1-bit and 2-bit storage mode according to the running application characteristics, such that write power and cache access performance can be improved.