沟槽型SiC-MOSFET相比平栅器件，导通电阻更小、功率密度更高、开关损耗更低。然而，由于存在沟槽界面电场集聚，SiC/SiO2界面势垒低、质量差等问题，沟槽型SiC-MOSFET面临严峻的可靠性挑战，其在电应力作用下的退化机理尚不明确，退化表征模型缺失。本项目将建立能全面表征沟槽型SiC-MOSFET界面损伤的探测新方法，在此基础上，深入研究沟槽型SiC-MOSFET在瞬时雪崩、瞬时短路、体二极管浪涌、ESD冲击等瞬时极限电应力下的失效机理，以及在动态栅极偏置、重复雪崩、重复短路、功率开关循环等长程电应力下的退化机理，进而建立一套不同电应力作用下的退化表征模型，准确评估器件寿命，为研制高可靠沟槽型SiC-MOSFET及其功率电子系统打下坚实的理论基础。

Compared with planar devices, trench SiC-MOSFETs take the advantages of lower ON-state resistance, higher power density and lower switching losses. However, due to the accumulation of electric field along the trench interface, and the poor quality and low barrier of SiC/SiO2 interface, trench SiC-MOSFETs are facing with severe reliability challenges. Nowadays, the degradation mechanisms for trench SiC-MOSFETs under various electrical stresses are unclear while the related degradation characterization models are still missing. A novel interfacial damage extraction method, which can reflect the degradations along the gate oxide interface for trench SiC-MOSFETs comprehensively and accurately, will be proposed in this project. Then the failure mechanisms under transient electrical stresses including single-pulse avalanche, single-pulse short-circuit, body diode surge and ESD stresses, and the degradation mechanisms under long-term electrical stresses including dynamic gate bias, repetitive avalanche, repetitive short-circuit and power cycling stresses for trench SiC-MOSFETs, will be investigated in details. Furthermore, based on the research results above, comprehensive degradation characterizations models, which can characterize the exact degradation trends and predict the lifetimes for trench SiC-MOSFETs suffer from various electrical stresses, will be established. This project will lay a solid theoretical foundation for the fabrication of high-reliable trench SiC-MOSFETs and power electronics systems employing them.