单片式像素探测器列级低功耗ADC读出技术研究

针对未来粒子对撞机的顶点探测器（Vertexing detector）和径迹探测器（Tracking detector），开展单片式像素探测器（MAPS）低功耗读出电路技术的研究。目前MAPS研发转向深亚微米CMOS工艺，主流的芯片结构针对顶点探测器的内层，采用小尺寸像素和二进制读出方式，空间分辨率高，但功耗较大。而对于外层的顶点探测和径迹探测，由于传感面积较大，要求芯片功耗更低。本项目针对探测器外层需求，优化改进像素探测器结构，适当增加像素的尺寸，并采用列级模数转换器（ADC）读出，在保证有效空间分辨率的前提下，降低芯片的功耗，并缩短芯片的积分时间。同时，ADC将采用自触发的工作模式，有效降低功耗。通过对列级低功耗ADC读出电路的设计研究，掌握MAPS像素探测器的前端电子学技术以及深亚微米工艺低功耗电路的设计方法，为今后实现高性能MAPS探测器奠定坚实的基础。

The topic of this project is the R&D of a low-power front-end readout circuit for Monolithic Active Pixel Sensors (MAPS) which will be used in the vertexing detector and tracking detector in the future collider. At present, the development of MAPS is based on the deep submicron CMOS process. The architecture of the state-of-the-art MAPS towards the inner lays of the vertex detector is mainly composed of a pixel array with small pixel pitch and the binary read-out circuit, and therefore having high spatial resolution and high power consumption. However, the outer layers of the vertex detector and tracker, which have the largest sensitive area of the total detector, require minimizing the power consumption of MAPS. This project towards the specifications of the outer layers will employ large pixel pith with an ADC converter at the end of each column. In this case, the number of pixels will be reduced, therefore reducing the integration time and power consumption. The loss in spatial resolution due to the sizeable pitch can be compensated by the column-level ADC. Also the ADC will be designed in a self-triggered operation mode to save power. All the efforts is to master the technical skills including the MAPS front-end electronics design and low power circuit design with deep submicron CMOS process, and also to build a solid foundation for the future design of high performance MAPS.