宽电压时序推测型高速缓存（Cache）电路与架构优化研究

为了缓解日益严重的“功耗墙”问题，越来越多的应用要求将工作电压扩展到包括近阈值在内的宽电压范围。然而，局部工艺波动导致近阈值区SRAM存储单元延迟分布较逻辑电路呈现更为严重的长尾特性（非高斯分布），使得SRAM性能急剧恶化。这也使主要由SRAM构成的Cache成为系统的性能瓶颈。围绕近阈值Cache性能优化，本课题突破传统方案中要求访存结果必须完全正确的限制，采用时序推测的思想，开展SRAM电路结构、SRAM访问故障模型与Cache性能/能耗模型、Cache架构优化三个层次的研究。所提出的交叉感知机制可以将近阈值下的SRAM吞吐量提升近一倍；统计学故障模型可以较传统蒙特卡洛仿真更快地评估任意大小存储阵列的故障率和访问延迟；Tag与Data阵列双重推测的Cache架构、PVT自适应频率调节技术及“弱”存储单元重映射机制等优化技术可以将Cache访问延迟降低近50%，访问能耗降低40%左右。

To mitigate the ever-worsening “Power Wall” problem, more and more applications need to expand their power supply to the wide-voltage range, which includes the near-threshold area. However, the delay distribution of SRAM bit cells under the near-threshold voltage shows a more serious long-tail (non-Gaussian) characteristic than that of logic circuits due to the local process fluctuation. This non-Gaussian delay distribution makes the SRAM performance degraded significantly, which, in turn, makes the SRAM based Cache a performance bottleneck of the system. To address the problem of Cache performance degradation under the near-threshold condition, we break through the limitation of all memory accesses must be fully correct. Instead, based on the idea of timing speculation, we conduct studies in the SRAM circuits, SARM accessing fault modeling and Cache performance/power models and Cache architecture optimizations as well. Compared to the conventional approach, the throughput of SRAM arrays under the near-threshold power supply can be boosted almost 1X by leveraging the proposed cross-sensing mechanism. The proposed statistical accessing fault model can be applied to evaluate the fault ratios and latencies of SRAM arrays with arbitrary sizes，which is much faster than the time-consuming Monte Caro simulations. The Cache architecture optimizations carried out in our studies, such as the Tag and data array double-speculation Cache architecture, the PVT aware Cache frequency adjusting technology and the “weak” sub-block remapping mechanism, can significantly lower the average Cache access latency about 50%, while the average energy consumption of each Cache access can also be reduced roughly 40%.