物理不可克隆函数(Physical Unclonable Function, PUF)电路，通过正向提取芯片制造过程中无法避免引入的工艺偏差，易产生具有随机性、唯一性以及防篡改特性的安全密钥，可广泛应用于信息安全领域。然而PUF电路在具体设计与应用时存在着全定制版图设计周期长、稳定性筛选成本高等方面的不足。鉴此，本项研究旨在通过对集成电路工艺偏差机理的研究，揭示PUF电路输出密钥的稳定性与工艺偏差的内在关系，探索PUF电路稳定性筛选新机制，提出PUF电路稳定性自主筛选方案，实现PUF电路自动编译。主要研究内容包括：稳定性自主筛选PUF电路模型构建；稳定性自主筛选PUF电路结构设计；稳定性自主筛选PUF电路自动编译；稳定性自主筛选PUF电路性能评测与优化等。研究成果将为高性能PUF电路的VLSI设计及稳定性筛选提供科学的理论依据和方法指导，促进PUF电路在信息安全领域的更好应用。

By extracting process deviations in the process of chip manufacturing, Physical Unclonable Function (PUF) circuit can easily generate security keys with characteristic of uniqueness, randomness and tamper-proof. PUF are being widely used in the field of information security. However, there are some shortcomings in the design and application of PUF circuit, such as long cycle of full customized layout design, high cost of stability screening. In view of this, this study aims to reveal the inherent relationship between the stability of PUF circuit output and process deviation by studying the mechanism of integrated circuit process deviation, explore the new mechanism of PUF circuit stability screening, propose stability autonomous screening scheme for PUF circuit, and realize automatic compilation of PUF circuit. The object of the research is stability autonomous screening of PUF circuit, and the main content includes the circuit's model construction, structure design, automatic compilation, and performance evaluation and optimization. The research results are expected to provide scientific theory and methodology for VLSI design and stability screening of high performance PUF circuit and to promote a better application of PUF circuit in the field of information security.