变异可识别的纳米负电容CMOS电路设计方法

以新机理、新结构和新材料为特征的超低功耗、陡亚阈摆幅(SS)负电容晶体管(NCFET)，为突破CMOS器件开关能耗瓶颈提供新途径。但是工艺变异引起的CMOS器件栅电容和铁电电容匹配的不确定性，导致NCFET在降低SS和消除滞回电压时形成两难困境，制约了负电容CMOS器件和电路的发展。..本项目通过负电容FinFET器件的工艺集成和多变异源融合，确定栅电容的离散分布和置信区间，结合沟道横向结构调整和双层铁电电容完成两个电容不同工作区域的精确匹配，确立无滞回电压SS极小值的边界，定义增益滞回电压比量化NCFET的效率与稳定性之间的关系。通过演算电路参数统计特征值的高阶秩，建立概率分布函数解析表达，以卡方检验验证统计分布的正确性，从而揭示负电容CMOS电路参数的统计规律。..项目实现了多变异源可识别的负电容CMOS电路设计和性能优化，提供了负电容CMOS电路参数估计和良率预测的可靠方法。

Ultra-low power steep sub-threshold swing (SS) negative capacitance transistor (NCFET), characterized by new mechanisms, new structures and new materials, provides an approach to break through the bottleneck of switching energy consumption in conventional CMOS devices. However, the uncertainty of gate capacitance and ferroelectric capacitance induced by process variations inherent in baseline CMOS devices leads to the dilemma between reducing SS and eliminating hysteresis voltage, which restricts the development of NCFET devices and circuits.. .In this project, the discrete distribution and confidence interval of gate capacitance are obtained by the fusion of different variation sources and process integration in negative capacitance FinFET. The capacitors are accurately matched by adjusting channel structure and double-layer ferroelectric capacitor in different operation regimes. The minimum of SS without hysteresis voltage is achieved; also the efficiency and stability of NCFET are quantified by definition of ratio of gain to hysteresis voltage. The statistical characteristics of negative capacitance CMOS are described by calculating the high-order statistical eigenvalues, establishing the probability distribution and its analytical expression, and using chi-square test to verify the correctness of statistical distribution...This project will realize variation-aware design and optimization of nanometer negative capacitance CMOS circuits with multiple variation sources, and provide a reliable method for the performance estimation and yield prediction of the negative capacitance CMOS circuits.