随着CMOS技术进入纳米工艺，沟道掺杂离子数下降为几十个，随机离散掺杂（RDD）成为影响集成电路性能和成品率的最重要波动源之一。对RDD的研究主要通过蒙特卡罗方法进行复杂费时的3D 器件分析，从电路设计方法看存在几个基本问题亟待解决：RDD效应如何引起电路性能变化？ 电路性能变化服从怎样的统计特性？什么方法可抑制RDD对电路的影响？. 项目通过精确捕获RDD的物理效应，由主成分分析将其特征化为BSIM 敏感模型参数，演算器件参数间的相关系数确定统计特征值进行函数映射，构建非正态概率密度函数Pearson IV的解析表达，实现电路参数变化特性的统计描述；通过增加本征沟道和背栅偏置技术抑制RDD对电路性能改变。. 本项目为RDD引起电路性能变化提供一种快速、精确的估计方法和兼顾成本、性能的抑制技术，为后摩尔时代单个掺杂离子背景下的CMOS电路设计提供理论和方法基础。

As CMOS technology is scaled to nanometer size, the number of doping atom in channel has decreased to dozens. Therefore, random discrete dopant (RDD) has become one of the most important variation sources which affect performance and yield of integrated circuit. However, current studies on RDD are mainly using the complicated and time-consuming 3D Monte Carlo simulation. There are several basic problems urgently to be solved from the point of view of circuit design methodology. They are: How does RDD effect affect the circuit performance? Which statistical characteristics does the circuit performance obey? What methodology can suppress RDD effects on circuit? . In this project, the physical effects of RDD are captured to accurately locate statistical distribution of doping atom, and it is characterized as SPICE BSIM model parameters by principal component analysis. The correlation coefficients between device parameters are calculated to determine the statistical characteristic values and functional mapping. Then the non-normal probability density function is realized and expressed to describe the statistical properties of RDD-induced circuit variations by Pearson IV distribution. At last, the RDD effect on circuit is suppressed by the added intrinsic channel and back gate bias technique. . This project provides a precise and fast estimation methodology for CMOS circuit variations due to RDD and a suppression technology considering tradeoff of cost and performance. It also provides a theoretical basis for the statistical design of CMOS circuit on the background of single doping transistor in post-Moore era.