多核系统芯片(MPSoC)高性能高并行性数据处理的发展趋势，使其软硬架构设计日趋复杂化。研究高效准确的性能评估技术是MPSoC软硬件系统架构探索与优化的关键，具有非常重要的现实意义。本项目以原始仿真(Native Simulation)和细粒度静态分析为主要技术手段，通过建立通信负载概率模型，将MPSoC软硬件系统的计算和通信性能评估有机统一起来，诣在提出针对整个MPSoC软硬件系统的高效准确性能评估技术。采用GCC剖析技术，基于代码覆盖率和软件交叉编译汇编代码，评估应用程序在目标平台的执行周期。构建高效灵活的层次化多级高速缓存架构模型，扩展高速缓存更新粒度；探索准确的指令/数据地址跟踪算法，准确映射目标平台存储器访问行为。建立通信负载概率模型，将通信数据按特定概率分布反馈回传输精确模型，评估架构的通信性能。通过本项目的研究，将为MPSoC软硬件架构系统级设计奠定有效的技术基础。

Requirements of high performance and parallel computations drive MPSoC design more complex. Efficient design of MPSoC requires early, fast and accurate performance estimation techniques. Basing on dynamic native-simulation and static fine-grained code analysis, new techniques are to be proposed to estimate accurate performance for MPSoC SW/HW architecture. A GCC profiling tool is applied in the native simulation process and based on the profiling result, an instruction analyzer of the target CPU architecture is proposed to analyze the cycle cost of C code under estimation. Configurable Multi-Level cache models are proposed to estimate cache miss penalty, and an innovative strategy will be adopted to update the cache status more efficiently. Furthermore, a dynamic simulation and static analysis combined method is presented to obtain the accurate address mapping in target platform. To estimate communication performance caused by communication conflicts and memory bandwidth, a Communication Overload Probability Model will be modeled to imitate data communication behavior of all processors to Transaction Accurate Model.