片上光网络架构设计和可靠性协同优化

基于硅光互连在带宽密度和功耗上的优势，近年来片上光网络成为了新一代众核处理器片上互连架构发展的重要方向。其中一个关键挑战是如何在片上光网络架构设计中充分考虑热光效应导致的可靠性问题，实现网络性能、功耗与可靠性的综合优化。本项目基于申请人在片上光网络架构设计、热光效应建模及系统级仿真方面丰富的前期研究基础，聚焦可靠性优化难点，开创性地开展片上光网络架构设计和可靠性协同优化。主要研究内容包括：1）面向异构众核处理器上通用处理器内核和硬件加速器不同的通信需求，进行片上光网络架构设计和通信机制优化；2）系统性开展片上光网络的可靠性优化方法研究，包括器件级到网络级的温度敏感性模型和基于强化学习的自适应路由算法；3）提出一种面向异构众核处理器的系统级综合仿真方法，集成处理器任务调度和通信负载仿真、片上光网络仿真、热光效应仿真及片上温度仿真，用于精确评估片上光网络在动态温度梯度下的性能、功耗与可靠性。

Because of advantages in bandwidth density and power efficiency, optical network-on-chip (NoC) based on silicon photonics has been proposed as an emerging on-chip communication architecture for many-core chip multiprocessors. One of the key challenges is how to alleviate the reliability problem in the architecture design of optical NoCs, in order to achieve the co-optimization of network performance, power efficiency and reliability. In this project, we will provide a systematic architecture design and reliability optimization approach of optical NoC. First, we will propose a systematic design and optimization approach of optical NoCs target for heterogeneous many-core chip multiprocessors. Second, we will propose a multi-level reliability optimization approach including thermal modeling and network-level learning-based routing optimization. At last, to accurately simulate the network performance, power efficiency and reliability of optical NoC under on-chip temperature gradient, we will propose a complete simulation platform which integrates processor task models, optical NoC simulator, optical thermal effect models, and on-chip temperature simulator.