近年来片上多核处理器成为嵌入式系统和高性能计算领域的重要平台。基于硅光互连的片上光网络被提出在未来的片上多核处理器中替代电互连，克服在功耗和带宽上的局限性。然而由于热光效应，片上光网络中波长选择性器件和激光器的波长对温度敏感。考虑到芯片上存在温度梯度，这些温度敏感性将导致额外的功耗。本课题将重点研究以下问题解决这一挑战：1）如何对片上光网络的温度敏感性进行系统级建模和分析；2）如何通过低温度敏感性设计方法和功耗优化技术解决温度敏感性难题；3）如何评估芯片上温度梯度对片上光网络功耗和性能的影响？本课题将提出一个参数化的片上光网络热效应分析平台；并以此为基础，提出高性能三维片上光网络的低温度敏感性设计和功耗优化技术，包括低温度敏感性光开关、低功耗路由算法和动态功耗控制；最后开发一套仿真平台评估新架构在芯片上温度梯度影响下的功耗和网络性能。本课题为解决片上光网络的温度敏感性问题有重要的研究意义。

The energy-efficient chip multiprocessor (CMP) is a natural platform for embedded systems and high-performance computing. In order to overcome limitations of traditional electronic interconnects in power efficiency and bandwidth density, optical networks-on-chip (ONoCs) based on silicon photonic interconnect have been proposed as an emerging on-chip communication architecture for future CMPs with multiple cores or many cores. However due to thermo-optic effect, wavelength-selective optical devices and lasers, which are widely used in ONoCs, have temperature-dependent wavelength shift. As a result, on-chip temperature variations will cause additional loss and power consumption. In order to help overcome the challenge of temperature sensitivity of ONoCs under on-chip temperature variations, this project will particularly provide a systematic design and optimization approach to tackle the following problems: 1) how to model and analyze the temperature sensitivity of ONoCs from a system-level perspective; 2) how to optimize the power consumption of ONoCs through low-temperature-sensitivity design methods and power optimization techniques; 3) how to evaluate and analyze the impact of on-chip temperature variations in the performance and power efficiency of ONoCs. This project will first investigate the thermal effect in ONoCs from a system-level perspective, and establish an optical thermal modeling platform. Based on the thermal analysis, this project will then propose a low-temperature-sensitivity design of a 3D ONoC with several power optimization techniques, including a low-temperature-sensitivity low-loss non-blocking optical switch, a low-power routing algorithm, and an adaptive power control mechanism. At last, this project will develop a complete simulation platform to evaluate the performance and power efficiency of the proposed 3D ONoC under on-chip temperature variations. Considering the big challenge of temperature sensitivity in ONoC design, the proposed low-temperature-sensitivity design and power optimization for ONoC is important and necessary.