基于LPCVD Si3N4双层叠栅结构的GaN MISHEMT栅可靠性研究

GaN MISHEMT是备受关注的新一代GaN基功率器件种类之一，LPCVD SiN因质量良好被公认为GaN MISHEMT最可靠的栅介质层材料，在其淀积之前引入低温生长的薄插入层介质(2~3nm)可以有效避免LPCVD工艺中的高温过程对GaN表面带来的损伤，提高器件的栅可靠性，但这种双层叠栅结构器件的栅介质经时击穿失效机制和阈值电压漂移机制不明确，栅可靠性问题有待改善。本项目拟针对基于LPCVD SiN双层叠栅结构GaN MISHEMT的栅可靠性问题进行研究：1、建立器件栅介质经时击穿失效机制模型，并明确导致该失效的缺陷态微观结构和物理信息；2、建立高压、高温恶劣条件下器件阈值电压漂移机制，给出在该严苛条件下使用器件应考虑的栅极电压安全工作范围。本项目的完成有利于解决GaN MISHEMT商业化进程中的关键性问题：器件失效性测试标准的建立和在实际使用过程中栅极驱动电路设计需要考量的方向。

GaN MISHEMT is one of the new generation of GaN based power devices and LPCVD SiN is recognized as the most reliable gate dielectirc material for GaN MISHEMT because of its good quality. The introduction of a thin insertion layer (2~3nm) before SiN deposition can effectively avoid the damage of GaN surface caused by the high temperature in LPCVD process and improve the gate reliability of the device. However, the gate time dependent dielectric breakdown (TDDB) failure mechanism and threshold voltage drift mechanism are not clear, and the gate reliability needs to be improved. This project will study the gate reliability of GaN MISHEMT based on double stacked gate structure: 1. The physical model of TDDB failure mechanism will be established, and the microstructure and physical information of defect state leading to the failure will be clarified; 2. The mechanism of threshold voltage drift of devices under high voltage and high temperature conditions will be established, and the safe operating range of gate voltage that should be considered when using devices under such severe conditions will be given. The completion of this project will help to solve the key problems in the commercialization process of GaN MISHEMT: the establishment of device failure test standards and the problem needs to be considered when designing the gate drive circuits of the device.