多约束条件下UTBB FD-SOI晶体管总剂量效应模型研究

UTBB FD-SOI工艺是下一代抗辐射集成电路设计的重要技术方向，特殊BOX层的存在使总剂量效应成为其抗辐射的“瓶颈问题”。基于总剂量效应模型可在设计阶段形成“设计-辐射损伤分析-设计改进”的快速反馈，实现抗辐射UTBB FD-SOI电路的高效设计。覆盖偏置、尺寸等多约束条件是模型建立的难点，而BOX层电场非均匀分布及本征缺陷密度波动又是UTBB FD-SOI总剂量效应模型研究面临新的科学问题。本项目以UTBB FD-SOI晶体管为研究对象，开展多约束条件下总剂量效应模型研究：测试完备的晶体管辐射损伤规律，以此为输入条件进行辐射损伤机理模拟仿真，综合仿真及试验结果，建立晶体管辐射损伤物理方程并进行参数拟合。本项目的创新点是针对BOX层非均匀电场分布，在三维尺度建立辐射损伤物理方程，并覆盖偏置、尺寸、阈值电压类型等多约束条件。本项目的实施可丰富辐射效应理论，为电路加固设计和评估提供支撑。

The UTBB FD-SOI process is an important technical direction for the design of next-generation radiation hardness integrated circuits. The presence of a special BOX layer makes the Total Ionizing Dose (TID) effect a “bottleneck issue” for its radiation hardness. Based on the TID model, rapid feedback of "design-radiation damage analysis-design improvement" can be formed in the design stage, and efficient design of radiation hardness UTBB FD-SOI circuit can be realized. Multi-constraint conditions such as irradiation bias condition and size are the difficulties in establishing the TID model, and the non-uniform distribution of the electric field in the BOX layer and the fluctuation of the intrinsic defect density are the new scientific problems faced by the UTBB FD-SOI TID model. This project takes the UTBB FD-SOI transistor as the research object, and carries out the research on the TID model under multi-constraint conditions: complete testing of the radiation damage law of the transistor, using this as the input condition to simulate the radiation damage mechanism, comprehensive simulation and test results, to establish the transistor radiation damage physical equation and parameter fitting. The innovation of this project is to establish the radiation damage physical equation at the three-dimensional scale for the non-uniform electric field distribution of the BOX layer, and cover multiple constraints such as bias condition, size, and threshold voltage type. The implementation of this project can enrich the theory of radiation effects and provide support for the design and evaluation of radiation hardness circuit.