A Systematic Methodology for Designing VLSI Systolic Arrays with Applications in Pattern Recognition and Image Processing

本研究以工程方法解决收缩阵列设计中的两个基本问题，即重构算法以增加并行性和有效地将算法映射到收缩阵列。现有转换系统的两个主要限制是不存在强大的系统语义转换和无法在最终设计中系统地实现最优性。正在努力研究：在复杂算法上的新的句法和语义转换，以优化收缩结构中的面积、时间、输入/输出和其他参数；将算法映射到具有反馈、复制数据、一般定时和有限或完全广播以及其他架构约束的二维或三维收缩数组的有效方法；收缩阵列宏管道的设计及其互联性、缓冲性、时序性、闭包性等相关问题并设计了用于图像处理和模式识别的收缩阵列宏管道。本研究的重点是理论方法和实践方法。随着理论的发展，自动化设计工具将被实现，以便它可以与现有的VLSI设计工具接口。

The research is an engineering approach to the solution of two fundamental problems in designing systolic arrays, namely, restructuring of algorithms for increased parallelism and efficient mapping of algorithms into systolic arrays. Two major limitations in the state-of-the-art of existing transformation systems are the nonexistence of powerful systematic semantic transformations and the inability to systematically achieve optimality in the resulting designs. Efforts are underway to investigate: new syntactic and semantic transformations on complex algorithms for optimizing area, time, input/output and other parameters in the systolic architecture; efficient methodology for mapping algorithms onto two- or three-dimensional systolic arrays with feedbacks, replicated data, general timing and limited or full broadcasting and other architectural constraints; design of macropipelines of systolic arrays and the related problems in interconnection, buffering, timing, and closure property; and design of macropipelines of systolic arrays for image processing and pattern recognition. Emphasis is on both theoretical and practical approaches in this research. With the theory developed, an automated design tool will be implemented so that it can be interfaced with existing VLSI design tools.