Support for Parallel Design in an Engineering Information System

随着复杂对象（如VLSI电路）设计的发展，许多子组件都是并行设计的。当子组件不能满足更高级别假定的规范时，冲突就会出现；当同一对象的两种不同表示（如电路和逻辑表示）由于一种表示的变化而在另一种表示中没有反映出来而变得不相等时，冲突也会出现。该研究项目将研究通过存储在工程信息系统中的信息自动检测冲突存在的技术，并将探索解决检测到的冲突的工具和方法。冲突识别的过程将以使用完整和正式正确的方法来识别和分类所有潜在的冲突为特征。冲突解决将依赖于人工智能技术，包括使用编码的启发式经验规则和必要的人工干预。本研究的目标是构建一个关于冲突检测、枚举、分类和最小化的正式结果的框架集，为VLSI设计过程量身定制，但适用于其他设计领域。

As the design of a complex object, such as a VLSI circuit, evolves, many subcomponents are designed in parallel. Conflicts can arise when subcomponents fail to meet the specifications that are assumed at a higher level, and conflicts can also arise when two different representations of the same object, such as the circuit and logic representations, become inequivalent due to changes in one representation that are not reflected in the other. This research project will investigate techniques for automatically detecting the presence of conflicts through the information stored in an engineering information system and will explore tools and methods for resolving detected conflicts. The process of conflict recognition will be characterized by the use of complete and formally correct methods to identify and classify all potential conflicts. Conflict resolution will rely on artificial intelligence techniques involving the use of encoded heuristic rules of thumb and human intervention as necessary. The goal of this research is to construct a skeletal set of formal results on conflict detection, enumeration, classification, and minimization, tailored to the VLSI design process but applicable to other design domains.