Performance Evaluation of Parallel Logic Programming Paradigms (Computer and Information Science)

建立了一个共享内存多处理器测试平台，用于测试并行逻辑编程语言体系结构。开发测试平台的目的是比较逻辑编程语言的几种并行实现，以确定哪种范型提供更高的成本效益性能。一个同样重要的目标是确定这些语言的内存特性和适合这些语言的内存设计。测试平台，使基准性能的经验测量，将由架构模拟器和内存模拟器运行在主机多处理器组成。处理器性能是根据所需的共享内存带宽来估计的，因为高速处理器最终受到内存带宽的限制，而需要更少带宽的架构具有更大的高性能潜力。要收集的内存性能统计信息包括本地缓存丢失率、流量比率、广播流量（保持缓存之间一致性所必需的）。这种方法最适合正在进行的处理器设计工作，如ICOT的PIM项目，因为实验内存设计可以快速描述，测试和结果与其他模型进行比较。该项目是与日本新一代计算机技术研究所（ICOT）合作完成的，由美国国家科学基金会/ICOT访问计划资助。

A shared memory multiprocessor testbed will be built for measuring parallel logic programming language architectures. The purpose of developing the testbed is to compare several parallel implementations of logic programming languages to determine which paradigm offers greater cost-effective performance. An equally important goal is the determination of the memory characteristics of, and memory designs suitable for those languages. The testbed, enabling empirical measurement of benchmark performance, will be composed of architecture emulators and memory simulators running on a host multiprocessor. Processor performance is estimated as required shared memory bandwidth because high speed processors are ultimately limited by memory bandwidth and architectures that require less bandwidth have greater potential for high performance. Memory performance statistics to be collected include local cache miss ratio, traffic ratio, broadcast traffic (necessary to retain consistency between caches). This methodology is most suited for ongoing processor design efforts, like the PIM project at ICOT, because experimental memory designs can be quickly described, tested and results compared with other models. This project is a collaborative effort with the Japanese Institute for New Generation Computer Technology (ICOT) and funded under the NSF/ICOT Visitors Program.