Implementation of Maximum Likelihood Decoding for Trellis Codes and Trellis Coded Modulation

一个最大似然维特比解码器的单芯片实现正在研究与卷积码和栅格编码调制使用。实际的最终设计和制造将在第三阶段进行。解码器匹配所有代码，最多有64个状态，分支将网格中的任何状态连接到最多4个新状态。该解码器芯片将广泛应用于数字通信系统和数字记录系统，包括磁、磁光和光学系统。该芯片有望用于高速电话线调制解调器、卫星通信和磁记录应用。最大似然解码器将显著降低先前使用卷积编码的信息比特流中信道诱导错误的发生率。虽然卷积编码器很容易实现，但构成维特比解码器的动态规划算法要困难得多，因此是一个非常重要的贡献。

A single chip implementation of a maximum likelihood Viterbi decoder is being studied for use with convolutional codes and trellis coded modulation. The actual final design and fabrication will occur in Phase III. The decoder is matched to all codes with up to 64 states with the property that branches connect any state in the trellis to at most 4 new states. This decoder chip will have extensive applications in digital communication systems and in digital recording systems including magnetic, magneto-optic and optical systems. This chip is expected to be of use in high-speed telephone-line modems, satellite communication, and magnetic recording applications. The maximum-likelihood decoder will significantly reduce the incidence of channel induced errors in the information bit stream, which was previously convolutionally encoded. While the convolutional encoder is easy to implement, the dynamic programming algorithm which constitutes the Viterbi decoder is much more difficult and is thus a very significant contribution.