Architectural Study of a Digital Signal Processing Multiprocessor Concept

新兴的数字信号处理（DSP） VLSI产品正在拓宽系统设计人员的视野。由于其紧凑的尺寸和低成本，紧密耦合的单板多处理器配置现在是相当可行的。本研究考察了通过明智地选择适合现代Very Long Instruction Word （VLIW）编译技术的体系结构，可以在多大程度上最小化硬件。考虑到解决DSP问题的需要，正在为涉及FFT、2D滤波和动态规划算法的少数关键DSP例程确定架构权衡。此外，自动指令调度/压缩技术也与体系结构选择有关。最终，预计所产生的结果将突出一些商用DSP芯片的优点和缺点。评论者给了它非常高的16分、18分和18分。所有的审稿人都认为这是一个优秀团队的高质量工作，源于创新的想法。第二期项目的发展潜力很大。成功将导致在仪器的理论和实践有意义的进步，需要信号处理电路的设计。

Emerging Digital Signal Processing (DSP) VLSI products are widening the horizons of system designers. Because of their compact size and low cost, tightly-coupled single-board multiprocessor configurations are now quite feasible. This research examines the degree to which hardware can be minimized by judicious selection of an architecture that lends itself to modern Very Long Instruction Word (VLIW) compilation techniques. With the need to solve DSP problems in mind, the architectural tradeoffs are being determined for a small number of critical DSP routines involving FFT's, 2D filtering, and dynamic programming algorithms. Also, automatic instruction scheduling/compaction techniques are being related to the architectural choices. Ultimately, it is expected that the results generated will highlight the strengths and weaknesses for some of the commercially- available DSP chips. Reviewers awarded this very high scores of 16, 18 and 18. All reviewers saw this as quality work stemming from innovative ideas to be done by an excellent group. There is high potential for a Phase II project. Success will lead to a meaningful advance in the theory and practice of instruments that require signal processing circuit design.