An Equivalent Circuit Model to Analyze Single-Event Upset in CMOS SRAMs

互补金属氧化物硅（CMOS）静态随机存取存储器（SRAM）单元的尺寸随着每一代SRAM阵列的引入而减小了两倍以上。为了设计SRAM单元，必须了解多余载流子产生对存储单元电路的瞬态影响。本研究旨在设计一种SRAM单元的等效电路模型，以模拟单元在单一事件扰动时的瞬态响应。该模型将进行数值和实验验证。应用于SRAM阵列的设计将被研究。

Complimentary metal oxide silicon (CMOS) static random access memory (SRAM) cells have decreased in size more than two times with the introduction of each new generation of SRAM array. Now the transient effects of excess carrier generation on the circuits of the memory cell must be understood in order to design the SRAM cells. The research is to design an equivalent circuit model of an SRAM cell which approximates the cell transient response during a single event upset. The model will be verified both numerically and experimentally. Applications to the design of SRAM arrays will be investigated.