A Bit-Parallel, Word-Parallel, Massively Parallel Associative Processor for Scientific Computing

经典的SIMD相联处理器以位串行字并行的方式执行算术。目前的大规模并行机还可以在细粒度计算环境中执行位串运算。这种位序列属性是提高处理速度的限制因素。基于经典的联想处理器模型，提出了一种简单但功能强大的新体系结构。通过在存储单元的片之间分布逻辑，使得多个位平面共享一个简单的逻辑单元，在大规模并行环境中的位并行运算变得可行。对于m位操作数，乘法等复杂运算的执行周期为O(M)，而位串行机的执行周期为O(M2)。该结构的简单性使其能够使用VLSI技术实现，从而允许构建字并行、位并行、大规模并行(P3)计算系统。提出的工作的主要目标是建立一个实验性的P3机器，它将嵌入到一个异质的超级计算环境中。对这种体系结构和实际工作原型的需求源于许多应用，而这些应用在传统的高级计算机中是不能解决的。在这项提案中，概述了空间科学的应用，因为这项工作也得到了NASA的支持。

Classical SIMD associative processors execute arithmetic in a bit- serial word-parallel manner. Current massively parallel machines also perform bit-serial arithmetic in a fine grain computing environment. This bit-serial property is a limiting factor in increasing processing speeds. A simple but powerful new architecture based on the classical associative processor model is proposed here. By distributing logic among slices of storage cells such that a number of bit-planes share a simple logic unit, bit- parallel arithmetic in a massively parallel environment becomes feasible. For m-bit operands, complex operations such as multiplications execute in O(m) cycle as opposed to O(m2) for bit- serial machines. The simplicity of the architecture enables its implementation using VLSI technology, and hence allows the construction of a word-Parallel, bit-Parallel, massively Parallel (P3) computing system. The main goal of the proposed work is to build an experimental P3 machine which is to be embedded into a heterogeneous supercomputing environment. The need for such architecture and for an actual working prototype stems from a number of applications which cannot be solved in conventional spercomputers. In this proposal, space science applications are outlined as this work is also supported by NASA.