RIA: Designing VLSI Arithmetic Arrays to Satisfy Precision Constraints

数字信号处理(DSP)结构由于有限字长效应而引入算术误差。不同的数字表示法和算术方法有其相关联的精度。这项研究提供了一个统一的框架，在这个框架下可以比较许多不同的设计方案。研究了在满足运算精度约束的同时最大化性能和最小化VLSI系统成本的各种VLSI结构。它使用统计状态空间模型来评估定点、浮点、带符号数字、剩余、对数和有理数系统以及分布式和CORDIC运算的精度。与传统微处理器不同，专用系统可以有多种不同的内部字长。适当字长的选择可以定义为一个整数优化问题，其中以运算精度为约束条件，以VLSI面积(A)、延迟(L)或周期(P)等系统代价的度量为目标函数。将构建CAD工具，以探索交替算法、体系结构和字长的巨大设计空间。

Digital signal processing (DSP) structures introduce arithmetic error due to finite wordlength effects. Different number representations and arithmetic methods have their associated precision. This research provides a unifying framework within which many different design alternatives can be compared. It studies various VLSI architectures which satisfy constraints on arithmetic precision while maximizing performance and minimizing VLSI system cost. It uses a statistical state-space model to evaluate the precision of fixed-point, floating -point, signed- digital, residue, logarithmic and rational number systems and distributed and CORDIC arithmetics. Unlike conventional microprocessors, dedicated systems can have a multitude of distinct internal wordlengths. The choice of an adequate wordlength can be defined as an integer optimization problem in which arithmetic precision is a constraint and some measures of system cost such as VLSI area (A), latency (L), or period (P), as the objective function. CAD tool will be built to explore the large design space of alternate arithmetic, architectures and wordlengths.