Topological and Physical Layout Design Techniques for Yield Enhancement

韩：这项研究是关于设计工具，可以弥补由于逻辑复杂性而造成的制造产量损失。初步结果表明，通过降低芯片对点缺陷的敏感性，可以提高成品率。产率优化算法和技术，适用于设计的最后两个阶段-拓扑/符号和物理布局正在探索。物理布局策略，以提高产量在通道路由和压缩阶段的标准电池设计正在研究。通过基于pla的设计来说明拓扑设计的产量增强。

Koren This research is on design tools which can compensate for manufacturing yield losses due to the complexity of the logic. Preliminary results have shown that yield can be enhanced by the technique of reducing the sensitivity of the chip to point defects. Yield optimization algorithms and techniques which are applicable to the last two stages of design - topological/symbolic, and physical layout are being explored. Physical layout strategies for yield enhancement in the channel routing and compaction phases for standard cell designs are being investigated. Yield enhancements in topological designs are being illustrated through PLA-based designs.