Techniques and Tools for Estimating and Improving the Yield and Reliability of VLSI Circuits

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Semiconductor manufacturing technologies now enable the placement of up to 50 million devices on one die, and allow clock speeds to approach the GHz range. These advances, however, are accompanied by larger yield losses (both catastrophic and parametric) and lower reliability. This project is on the development of techniques for improved yield-reliability estimation and enhancement. These techniques include hierarchical yield estimation and enhancement, minimum perturbation approach for yield and reliability enhancement and new methods for crosstalk and electromigration minimization. The tradeoffs among yield, reliability and other optimization goals such as speed and area, are being investigated as well. This research emphasizes the integration of the yield and reliability enhancement objectives with the primary goals of performance and area, while keeping design data volumes manageable. A major focus of the project is on proving the advantages of the new techniques by implementing and integrating them into existing design frameworks.